一位全加器的行为描述程序Library IEEE; -IEEE 标准资源库，Use IEEE.std_logic_1164.all; -常用数据类型和函数定义Entity full_adder is port(x,y,Cin:in std_logic;sum,Cout:out std_logic);End full_adder;Architecture a_adder of full_adder isBegin process variable N :integer;constant sum_vector:bit_vector(0 to 3):=“0101”;constant Cout_vector:bit_vector(0 to 3):=“0011”;Begin wait on x,y,Cin; -注释等待输入信号变化N:=0; -N 赋初值 0if x=1 then -由此N:=N+1;end if;if y=1 thenN:=N+1;end if;if Cin=1 thenN:=N+1;end if; -到此，统计 1 的个数，决定输出Sum0)and(i1 then rut(i):=1; -例如，256/128=21,则 rut(7)=1;din:=din-rig;elserut(i):=0;end if;rig:=rig/2; -参照值除以 2end loop;return rut;end nat_to_bit8;end n_pack;Rs 触发器行为描述 Library ieee;use ieee.std_logic_1164.allEntity rsff isport( s, r : in std_logic;nq,q :out std_logic);End rsff;Architecture const of rsff isbeginp1:processvariable l_state:std_logic :=0;beginAssert not(r=1 and s=1)report both r and s equal to 1severity Error;if r=1 and s=0 thenl_state:=0;elsif r=0 and s=1 thenl_state:=1;q=l_state;nq=not l_state;wait on s,r;end if;end process;end const;