TSK52x MCU Summary Core Reference CR0116 (v1.2) November 03, 2004 The TSK52x is a fully functional, 8-bit microcontroller, incorporating the Harvard architecture. This core reference includes architectural and hardware descriptions, instruction sets and on-chip debugging functionality for the TSK52x family. The TSK52x is an 8-bit embedded controller that executes all ASM51 instructions and is instruction set compatible with the 80C31. Features Control Unit 8-bit Instruction decoder Reduced instruction cycle time up to 12 times. Arithmetic-Logic Unit 8 bit arithmetic and logical operations Boolean manipulations 8 x 8 bit multiplication and 8 / 8 bit division. 32-bit Input/Output ports Four 8-bit I/O ports Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051. Interrupt Controller Four Priority Levels 7 external interrupts Internal Data Memory interface Can address up to 256 B of Data memory Space. CR0116 (v1.2) November 03, 2004 1 TSK52x MCU 2 CR0116 (v1.2) November 03, 2004 External Memory interface Can address up to 64 KB of external Program memory space Can address up to 64 KB of external Data memory space De-multiplexed Address/Data Bus to allow easy connection to memories Variable length code fetch and MOVC to access fast/slow Program memory Variable length MOVX to access fast/slow RAM or peripherals Wishbone-compliant (TSK52B_W and TSK52B_WD only) Performance The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. The TSK52x uses 1 clock cycle per machine (instruction) cycle. This leads to a more enhanced and efficient performance with respect to the industry standard 8051 processor working with the same clock frequency (in fact, the execution of instructions is an average eight times faster on the TSK52x). The standard 8051 has a 12-clock architecture. A machine (instruction) cycle needs 12 clock cycles to execute to completion and most instructions require either one or two machine cycles. Therefore, with the exception of MUL and DIV, the 8051 uses either 12 or 24 clock cycles for each instruction. Furthermore, each cycle in the 8051 uses two memory fetches. In many cases the second fetch is dummy and extra clock cycles are wasted. Table 1 Table 1. Speed advantage summary below shows the speed advantage of the TSK52x over the standard 8051. A speed advantage of 12 means that the TSK52x performs the same instruction twelve times faster that the 8051. Speed advantage Number of instructionsNumber of opcodes 24 1 1 12 27 83 9.6 2 2 8 16 38 6 44 89 4.8 1 2 4 18 31 3 2 9 Average: 8.0 Sum: 111 Sum: 255 The average speed advantage is 8.0. However, the real speed improvement seen in any system will depend on the mixture of instructions used. TSK52x MCU CR0116 (v1.2) November 03, 2004 3 Available Devices The following two variants of the microcontroller are available: TSK52A - Standard version of the core TSK52B_W - Wishbone-compliant version of the core In addition, a corresponding debug-enabled (OCD) version of each variant is also available (TSK52A_D and TSK52B_WD respectively). Note: Throughout this document, differences between core variants are listed in terms of the standard core devices (TSK52A and TSK52B_W). Unless specified otherwise, the feature/description applies to the debug-enabled version of the variant (TSK52A_D and TSK52B_WD) in exactly the same way. These devices can be found in the FPGA Processors integrated library (Program FilesAltium2004LibraryFpgaFPGA Processors.IntLib). TSK52x MCU Architectural overview Symbols Figure 1. TSK52x family symbols 4 CR0116 (v1.2) November 03, 2004 TSK52x MCU CR0116 (v1.2) November 03, 2004 5 Pin description The pinout of the TSK52x has not been fixed to any specific device I/O, thereby allowing flexibility with user application. The TSK52x contains only unidirectional pins - inputs or outputs. To simplify using the bidirectional ports (PORT0-3), the schematic symbol includes a bus pin for each direction, allowing them to be wired independently. Configuration of bus direction is performed under program control. Table 2. TSK52x Pin description Name Type Polarity/Bus size Description Control Signals CLK I Rise External system clock (used for internal clock counters and all other synchronous circuitry) CLK90 I Rise Second external clock with a phase lag of 90 Degrees in relation to CLK. RST I High External system reset. A high on this pin while the external system clock (CLK) is running resets the device WAIT_CPU1 I High When this signal is active, operation of the CPU is halted. Interrupt Signals INT0 I High/Rise External interrupt 0 INT1 I High/Rise External interrupt 1 INT2 I Fall/Rise External interrupt 2 INT3 I Fall/Rise Exter