Quartus II Software Design Series: Timing Analysis,- Timing analysis basics,2,Objectives,Display a complete understanding of timing analysis,3,How does timing verification work?,Every device path in design must be analyzed with respect to timing specifications/requirements Catch timing-related errors faster and easier than gate-level simulation & board testing Designer must enter timing requirements & exceptions Used to guide fitter during placement & routing Used to compare against actual results,IN,CLK,OUT,combinational delays,CLR,4,Timing Analysis Basics,Launch vs. latch edges Setup & hold times Data & clock arrival time Data required time Setup & hold slack analysis I/O analysis Recovery & removal Timing models,5,Path & Analysis Types,Three types of Paths: Clock Paths Data Path Asynchronous Paths*,Clock Paths,Async Path,Data Path,Async Path,Two types of Analysis: Synchronous clock & data paths Asynchronous* clock & async paths,*Asynchronous refers to signals feeding the asynchronous control ports of the registers,6,Launch & Latch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge: the edge which “launches” the data from source register Latch Edge: the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle),7,Setup & Hold,Setup: The minimum time data signal must be stable BEFORE clock edge Hold: The minimum time data signal must be stable AFTER clock edge,Valid,DATA,CLK,DATA,Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.,8,Data Arrival Time,Data Arrival Time = launch edge + Tclk1 + Tco +Tdata,CLK,Launch Edge,The time for data to arrive at destination registers D input,Comb. Logic,9,Clock Arrival Time,Clock Arrival Time = latch edge + Tclk2,CLK,Latch Edge,The time for clock to arrive at destination registers clock input,Comb. Logic,10,Data Required Time - Setup,Data Required Time = Clock Arrival Time - Tsu - Setup Uncertainty,CLK,Latch Edge,The minimum time required for the data to get latched into the destination register,Data must be valid here,Comb. Logic,11,Data Required Time - Hold,Data Required Time = Clock Arrival Time + Th + Hold Uncertainty,CLK,Latch Edge,The minimum time required for the data to get latched into the destination register,Data must remain valid to here,Comb. Logic,12,Setup Slack,The margin by which the setup timing requirement is met. It ensures launched data arrives in time to meet the latching requirement.,CLK,Launch Edge,Latch Edge,Comb. Logic,13,Setup Slack (contd),Positive slack Timing requirement met Negative slack Timing requirement not met,Setup Slack = Data Required Time Data Arrival Time,14,Hold Slack,The margin by which the hold timing requirement is met. It ensures latch data is not corrupted by data from another launch edge.,CLK,Latch Edge,Next Launch Edge,Comb. Logic,15,Hold Slack (contd),Positive slack Timing requirement met Negative slack Timing requirement not met,Hold Slack = Data Arrival Time Data Required Time,16,FPGA/CPLD or ASSP,ASSP or FPGA/CPLD,I/O Analysis,Analyzing I/O performance in a synchronous design uses the same slack equations Must include external device & PCB timing parameters,CL*,Tdata,Tclk1,Tclk2,OSC,Data Arrival Path,Data Arrival Path,Data Required Path,* Represents delay due to capacitive loading,17,Recovery & Removal,Recovery: The minimum time an asynchronous signal must be stable BEFORE clock edge Removal: The minimum time an asynchronous signal must be stable AFTER clock edge,CLK,ASYNC,18,Asynchronous = Synchronous?,Asynchronous control signal source is assumed synchronous Slack equations still apply data arrival path = asynchronous control path Tsu Trec; Th Trem External device & board timing parameters may be needed (Ex. 1),ASSP,FPGA/CPLD,OSC,FPGA/CPLD,Example 1,Example 2,Data arrival path,Data arrival path,Data required path,Data required path,19,Why Are These Calculations Important?,Calculations are important when timing violations occur Need to be able to understand cause of violation Example causes Data path too long Requirement too short (incorrect analysis) Large clock skew signifying a gated clock, etc. TimeQuest timing analyzer uses them Equations to calculate slack Terminology (launch and latch edges, Data Arrival Path, Data Required Path, etc.) in timing reports,20,Timing Models in Detail,Quartus II software models device timing at two PVT conditions by default Slow Corner Model Indicates slowest possible performance for any single path Timing for slowest device at maximum operating temperature and VCCMIN Fast Corner Model Indicates fastest possible performance for any single path Timing for fastest device at minimum operating temperature and VCCMAX Why two corner t