现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好! EtronTech EM68B16CWPA Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. 32M x 16 bit DDRII Synchronous DRAM (SDRAM) Etron Confidential Preliminary (Rev 1.4 Mar. / 2009) Features JEDEC Standard Compliant JEDEC standard 1.8V I/O (SSTL_18-compatible) Power supplies: VDD accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS# latency, and speed grade of the device. Table 1. Ordering Information Part Number Clock FrequencyData Rate Power Supply Package EM68B16CWPA-25H 400MHz 800Mbps/pinVDD 1.8V, VDDQ 1.8V FBGA EM68B16CWPA-3H 333MHz 667Mbps/pinVDD 1.8V, VDDQ 1.8V FBGA WP: indicates FBGA package A: indicates generation code H: indicates Pb and Halogen Free for FBGA Package EtronTech EM68B16CWPA Etron Confidential 2 Rev. 1.4 Mar. 2009 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 400 MHz 6 15 15 DDR2-800 400 MHz 5 12.5 12.5 DDR2-667 333 MHz 5 15 15 Figure 1. Ball Assignment (FBGA Top View) A B C D E 123789 VDDNC DQ14VSSQ VDDQDQ9 DQ12VSSQ VDDNC VSS UDM VDDQ DQ11 VSS . VSSQUDQS# UDQSVSSQ VDDQDQ8 DQ10VSSQ VSSQLDQS# VDDQ DQ15 VDDQ DQ13 VDDQ F DQ6VSSQLDMLDQSVSSQDQ7 G VDDQDQ1VDDQVDDQDQ0VDDQ H DQ4VSSQDQ3DQ2VSSQDQ5 J VDDLVREFVSSVSSDLCKVDD K CKEWE#RAS#CK#ODT L NCBA0BA1CAS#CS# M A10A1A2A0VDD N VSSA3A5A6A4 P A7A9A11A8VSS R VDDA12NCNCNC EtronTech EM68B16CWPA Etron Confidential 3 Rev. 1.4 Mar. 2009 Figure 2. Block Diagram CK# CKE CS# RAS# CAS# WE# DLL CLOCK BUFFER COMMAND DECODER COLUMN COUNTER CONTROL SIGNAL GENERATOR ADDRESS BUFFER REFRESH COUNTER 8M x 16 CELL ARRAY (BANK #0) Row Decoder 8M x 16 CELL ARRAY (BANK #1) Row Decoder 8M x 16 CELL ARRAY (BANK #2) Row Decoder 8M x 16 CELL ARRAY (BANK #3) Row Decoder Column Decoder Column Decoder Column Decoder Column Decoder MODE REGISTER A10/AP A9 A11 A12 BA0 BA1 A0 CK DATA STROBE BUFFER LDQS LDQS# UDQS UDQS# DQ Buffer LDM UDM DQ15 DQ0 ODT EtronTech EM68B16CWPA Etron Confidential 4 Rev. 1.4 Mar. 2009 Figure 3. State Diagram (E)MRS Setting MR, EMR(1) EMR(2) EMR(3) OCD calibration Initialization Sequence Idle All banks precharged Self Refreshing Refreshing Precharge Power Down Activating Active Power Down Bank Active Writing Writing With Autoprecharge Precharging Reading With Autoprecharge Reading ACT CKEL CKEH CKEL WR RDA RDA WRA WRA WR RD RD PR, PRA PR, PRA PR, PRA RDA WRA CKEL CKEH CKEL SRF CKEH REF CKEL WR RD PR CKEL CKEL Automatic Sequence Cammand Sequence CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down,exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) (E)MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail. EtronTech EM68B16CWPA Etron Confidential 5 Rev. 1.4 Mar. 2009 Ball Descriptions Table 3. Ball Descriptions Symbol Type Description CK, CK# Input Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains LOW. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A12 Input Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge). CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are ma