1.5 CMOS FABRICATION AND LAYOUT23 1.5CMOS Fabrication and Layout Now that we can design logic gates and latches from transistors, let us consider how the transistors are built. Transistors are fabricated on thin silicon wafers that serve as both a mechanical support and an electrical common point called the substrate. We can under- stand the physical layout of transistors from two perspectives. One is the top view, obtained by looking down on a wafer. The other is the cross-section, obtained by slicing the wafer through the middle of a transistor and looking at it edgewise. We begin by look- ing at the cross-section of a complete CMOS inverter. We then look at the top view of the same inverter and defi ne a set of masks used to manufacture the different parts of the inverter. The size of the transistors and wires is set by the mask dimensions and is limited by the resolution of the manufacturing process. Continual advancements in this resolution have fueled the exponential growth of the semiconductor industry. Figure 1.33 shows a cross-section of the inverter from Section 1.4.1. In this diagram, the inverter is built on a p-type substrate. The pMOS transistor requires an n-type body region, so an n-well is diffused into the substrate in its vicinity. Note that it is also possible to design a CMOS process with an n-type substrate and p-wells to contain the nMOS transistors. As described in Section 1.3, the nMOS transistor has n-type source and drain regions and a polysilicon gate over a thin layer of silicon dioxide (SiO2, also called gate oxide). The pMOS transistor is a similar structure with p-type source and drain regions. The polysilicon gates of the two transistors are tied together somewhere off the page and form the input A.The source of the nMOS transistor is connected to a metal ground line and the source of the pMOS transistor is connected to a metal VDD line. The drains of the 1.5.1 Inverter Cross-section 1 1 1 1 2 2 2 2 2 1 QM Q D CMOS fl ip-fl op with two-phase nonoverlapping clocks FIG 1.32 Weste01.fm Page 23 Sunday, January 4, 2004 10:32 PM CHAPTER 1 INTRODUCTION24 two transistors are connected with metal to form the output Y. A thicker layer of SiO2 called fi eld oxide prevents metal from shorting to other layers except where contacts are explicitly etched. The substrate must be tied to a low potential to avoid forward-biasing the p-n junc- tion between the p-type substrate and the n+ nMOS source or drain. Likewise, the n-well must be tied to a high potential. This is generally done by adding heavily doped substrate and well contacts, or taps, to connect GND and VDDto the substrate and n-well, respec- tively, as shown in Figure 1.34. The heavy doping is required to establish a good ohmic con- tact that provides low resistance for bidirectional current fl ow; a metal to lightly doped semiconductor junction forms a Schottky diode. For all their complexity, chips are amazingly inexpensive because all the transistors and wires can be printed in much the same way as books. The fabrication sequence consists of 1.5.2 Fabrication Process n+ p-substrate p+ n-well n+p+ nMOS TransistorpMOS Transistor FIG 1.33 n+ p-substrate p+ n-well A Y GND VDD n+p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS TransistorpMOS Transistor Inverter cross-section FIG 1.33 n+n+ p-substrate p+ n-well A Y GND VDD p+ Substrate TapWell Tap n+p+ Inverter cross-section with well and substrate contacts FIG 1.34 Weste01.fm Page 24 Sunday, January 4, 2004 10:32 PM 1.5 CMOS FABRICATION AND LAYOUT25 a series of steps in which layers of the chip are defi ned through a process called photoli- thography. Because many entire chips are printed at once, the cost of the chip is propor- tional to the chip area, rather than the number of transistors. As manufacturing advances allow engineers to build smaller transistors and place more transistors in the same area, each transistor gets cheaper. Smaller transistors are also faster because electrons dont have to travel as far to get from the source to the drain! This explains the remarkable trend for computers and electronics to become both cheaper and more capable with each generation. The inverter could be defi ned by a hypothetical set of six masks: n-well, polysilicon, n+ diffusion, p+ diffusion, contacts, and metal (for fabrication reasons discussed in Chap- ter 3, the actual mask set is usually different). Masks specify where the components will be manufactured on the chip. Figure 1.35(a) shows a top view of the six masks. The cross- section of the inverter from Figure 1.34 was taken along the dashed line. Consider a very simple fabrication process to illustrate the fundamental ideas. The process begins with the creation of an n-well on a bare p-type silicon wafer. Figure 1.36 shows cross-sections of the wafer after each processing step involved in forming the n- well; Figure 1.36(a) illustrates the bare substrate before processing. Forming the n-well requires ad