湖南大学 硕士学位论文 时延故障测试产生算法与I测试实验研究 姓名：蔡烁 申请学位级别：硕士 专业：信号与信息处理 指导教师：邝继顺 20070413 硕士学位论文 - I- 摘摘 要要 随着集成电路设计与加工技术的飞速发展，测试作为 IC 产业中一个极为重 要的环节，变得越来越困难。特别是进入深亚微米发展阶段以来，通过集成各种 IP 核，系统级芯片的功能更加强大，同时也带来了一系列的测试问题。 工业界常采用电压测试和稳态电流测试方法来测试数字 CMOS IC。电压测 试的方法比较简单， 速度快， 它对于检测固定型故障是有效的， 但对于检测 CMOS 工艺中的其他类型故障则显得有些不足。20 世纪 80 年代初，人们提出了用测量 CMOS 电路稳态电流的方法来测试集成电路，但随着深亚微米技术的发展，这种 方法的局限性也暴露出来，如测试速度慢、故障与正常电流的差别变小等。 90 年代中期，人们提出了瞬态电流测试的方法，试图通过分析正常电路和 故障电路在两次稳定状态之间电流变化过程的不同来发现一些其他测试方法所 不能发现的故障，以进一步提高故障覆盖率。本文在瞬态电流测试已有算法的基 础上，针对门时延故障模型，提出了一种基于 3 个向量的测试产生算法。实验表 明产生的向量能有效的检测时延故障。 为了进一步验证瞬态电流测试方法的理论， 本文着手对具体电路的瞬态电流 进行测量。对给定电路 C432 的 3 个特定故障：168 点开路故障、444 点固定为 1 的故障以及 264 点时延故障，对其作测试产生，把产生的向量施加到电路原始输 入端，并尝试着在实验电路板上测量电路电源电流 的值，从而期望通过实验的 方法来指导理论研究工作。 可测性设计是现代电路测试中的一种重要方法。 本文实现了一种基于自反馈 的测试向量产生方法，采用只增加反馈线的方式来对集成电路进行测试。该方法 以减少测试时间、芯片面积和存储开销为目的，对于可测性设计的发展有较大的 现实意义。 关键词：关键词：测试产生算法；IDDT 测试；时延故障；可测性设计；自反馈 时延故障测试产生算法与 IDDT测试实验研究 -II- Abstract With the rapid development of the designing and machining technology of IC , testing becomes more and more difficult. It is considered to be a very important part in IC industry. Especially after IC industry entering deep submicron stage of development, by integrating many kinds of IP core, the function of SOC becomes stronger and stronger, but the rapid development also brings in a series of problems. Voltage based testing and quiescent power supply current testing are typical test methods for digital CMOS ICs. Voltage based testing can detect many defects in a simple and fast way. it is effective in detecting stuck-at fault, but a little deficient in detecting other types of faults for CMOS ICs. In the early 1980s, quiescent power supply current testing method was proposed for CMOS testing. However, with the development of deep submicron designs, the limitations of this method, such as slow testing rate, small difference between faulty circuits and fault-free circuits, also become apparent. In order to improve the fault coverage, the dynamic current testing was proposed in the middle 1990s. By analyzing the changing process of transient current between two steady statuses of faulty circuits and fault-free circuits, it can detect some faults that cannot be detected by other testing methods. Based on the existent IDDT testing algorithm, a test generation algorithm for gate delay faults is presented, having three test patterns. The experimental results show that the algorithm is effective. To further validate the theories of IDDT testing, the IDDT of real circuits is measured. Given a C432 circuit with three special faults: stuck-open fault in node 168, s-a-1 fault in node 444 and delay fault in node 264, the faults are tried to be detected by means of giving test patterns to the primary inputs and measuring the power supply current of the experimental circuit board, with the hope that the experimental results can guide the theory research task. Design for testability is an important method in IC testing. A test pattern generator based on CUTs feedback is realized. To minimize the test times, chip areas and storage space, the presented method tests IC only by adding some feedback lines. Key Words: test generation algorithm；IDDT testing；delay fault；design for testability(DFT) ；feedback 硕士学位论文 - III- 插图索引插图索引 图 1. 1 电压测试原理.2 图 1. 2 CMOS 反相器中的缺陷与 IDDQ.3 图 1. 3 瞬态电流测试基本原理 .4 图 1. 4 全速电流测试方法示意图 .6 图 2. 1 随机测试向量数与故障覆盖率的关系.9 图 2. 2 一个单固定型故障的例子 .10 图 2. 3 有冗余故障的电路 .11 图 2. 4 CMOS 与非门电路图.12 图 2. 5 波形模拟算法流程图.17 图 3. 1 瞬态电流测试方法示意图.19 图 3. 2 电压法测时延故障示意图 .19 图 3. 3 瞬态电流法测时延故障示意图.20 图 3. 4 算法流程图 .22 图 3. 5 节点波形图 .23 图 3. 6 C17 电路图.24 图 3. 7 C17 正常电路 16 号节点波形 .26 图 3. 8 C17 故障电路 16 号节点波形 .26 图 3. 9 C17 正常电路 7、9 号节点波形 .26 图 3. 10 C17 故障电路 7、9 号节点波形 .27 图 3. 11 C17 正常电路瞬态电流波形 .