BLDC Motor Speed Estimation Using PDC Timer Module1 Speed Calculation of BLDC 1.1 Summary of BLDCSince current BLDC has substituted the electrical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic disturbance, short lifetime, etc. Now BLDC is provided with advantages of simple structure, dependable operation and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor does. So it is widely used in various fields of industrial control now.1.2 PDC Module Introduction SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC) timers used for capture function and PWM operation. It also supports position detection features for Brushless-DC motor application. The PDC timers are very suitable for both mechanical speed calculation, with ACI and BLDC motor included, and phase commutation for changing current conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For details of PDC timers specification, please refer to Table 1-1.Table 1-1 PDC TimerFunction PDC Timer 0 PDC Timer 1 Clock sources Internal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKBInternal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKB IO pins TIO0A, TIO0B, TIO0C TIO1A, TIO1B, TIO1C Timer general register P_TMR0_TGRA, P_TMR0_TGRB, P_TMR0_TGRC P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC Timer buffer register P_TMR0_TBRA, P_TMR0_TBRB, P_TMR0_TBRC P_TMR1_TBRA, P_TMR1_TBRB, P_TMR1_TBRC Timer period and counter register P_TMR0_TPR, P_TMR0_TCNT P_TMR1_TPR, P_TMR1_TCNT Capture sample clock Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Counting edge Count on rising, falling, both edge Count on rising, falling, both edge Counter clear source Cleared on P_TMR0_TGRA, P_TMR0_TGRB, P_TMR0_TGRC capture input. Cleared on P_POS0_DectData position detection data changes. Cleared on P_TMR0_TPR compare matches. Cleared on P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC capture input. Cleared on P_POS1_DectData position detection data changes.Cleared on P_TMR1_TPR compare matches. Input capture function Yes Yes PWM compare match output function 1 output Yes Yes 0 output Yes Yes Output Hold Yes Yes Edge-aligned PWM Yes Yes Center-aligned PWM Yes Yes Phase counting mode Yes, phase inputs are TCLKA/TCLKB Yes, phase inputs are TCLK C/TCLKD Timer buffer operation Yes Yes AD convert start trigger P_TMR0_TGRA compare match P_TMR1_TGRA compare matchInterrupt sources Timer 0 TPR interrupt Timer 0 TGRA interrupt Timer 0 TGRB interrupt Timer 0 TGRC interrupt Timer 0 PDC interrupt Timer 0 overflow interrupt Timer 0 underflow interrupt Timer 1 TPR interrupt Timer 1 TGRA interrupt Timer 1 TGRB interrupt Timer 1 TGRC interrupt Timer 1 PDC interrupt Timer 1 overflow interrupt Timer 1 underflow interrupt Figure 1-1 PDC Timers Block Diagram 1.3 PDC Operation This note mainly depicts PDC application in motor speed measurement. For detailed PDC introduction, please refer to “SPMC75F2413A Programming Guide” authored by Sunplus. PDC module has four types of registers to perform speed measurement: Timer control register P_TMRx_Ctrl (x = 0, 1), position detection control register P_POSx_DectCtrl (x = 0, 1), input output control register P_TMRx_IOCtrl (x = 0, 1), and timer interrupt enable register P_TMRx_INT (x = 0, 1). Where, P_TMRx_Ctrl and P_POSx_DectCtrl are introduced in detail. 1.31Input Output Control Register P_TMRx_Ctrl(x = 0, 1) B15 B14 B13 B12B11 B10 B9 B8 R/W R/WR/WR/WR/WR/WR/WR/W 0 0 0 0 0 0 0 0 SPCK MODE CLEGS B7 B6 B5 B4 B3 B2 B1 B0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPCK MODE CLEGSBit 15:14 SPCK: Capture input sample clock select. These bits select the capture input sample clock. Capture input will be sampled with sample clock. Pulses shorter than four sample clocks will be considered invalid, and will be ignored.00 = FCK/1 01 = FCK/210 = FCK/4 11 = FCK/8Bit 13:10 MODE: Modes select. These bits are used to select the timer operation modes. 0000 = Normal operation (continuous counter up counting) 0100 = Phase counting mode 1 0101 = Phase counting mode 2 0110 = Phase counting mode 3 0111 = Phase counting mode 4 1x0x = Edge-aligned PWM mode (continuous counter up counting, PWM output) 1x1x = Center-aligned PWM mode (continuous counter up/down counting, PWM output)Bit 9:8 CLEGS: Counter clear edge select. These bits select