PLD,JTAG interface,Reference,AN 39: JTAG Boundary-Scan Testing in Altera Devices Altera Co. AN 88: Using the Jam Language for ISP & ICR via an Embedded Processor Altera Co. IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-2001 (Revision of IEEE Std 1149.1-1990),What is JTAG?,JTAG Joint Test Action Group BST A standard Boundary-Scan Testing interface,Why JTAG?,A uniform interface for device testing Daisy chain structure to testing multiple IC from one testing interface On-line testing and programming Provides extra function such as CPU debugging and board bus control,History of JTAG,1985 Joint European Test Action Group(JETAG) was formed in Europe 1986 The group expanded to include members from both Europe and North America and was renamed the Joint Test Action Group (JTAG). 1988 JTAG Version 2.0was offered to the IEEE Testability Bus Standards Committee (P1149) 1993 IEEE Std 1149.1a-1993,Boundary-scan Testing,Feature of BST,Offers the capability to efficiently test components on PCBs with tight lead spacing. Test pin connections without using physical test probes and capture functional data while a device is operating normally. Force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results.,BST Pins for Altera MAX7000A,Description of BST Pins,Functional Model IEEE Std. 1149.1 Circuitry,Registers of BST,Boundary-scan Register which is a shift register composed of all the boundary-scan cells of the device. Bypass Register which is a 1-bit-long data register used to provide a minimum-length serial path between TDI and TDO Instruction Register which is used to determine the action to be performed and the data register to be accesse,Test clock input pin (TCK),Many parts of the test logic perform operations in response to the rising or falling edge of TCK Be driven by a free-running clock with a nominal 50% duty cycle May vary significantly in frequency from one component to the another,Test mode select input (TMS),The signal received at TMS is decoded by the TAP controller to control test operations. TMS shall be sampled by the test logic on the rising edge of TCK. Change the signal driven to the TMS inputs of connected components on the falling edge of TCK. Design TMS pin carefully to avoid entering test mode by a voltage on un-driven TMS pin. A pull-up resistor is recommended,Test data input (TDI),Serial test instructions and data are received by the test logic at TDI. Signal presented at TDI shall be sampled into the test logic on the rising edge of TCK. The bus master will change the signal driven to the TDI input on the falling edge of TCK. The design of the circuitry should ensure that an un-driven input produces a logic 1. (Pull-up resistor),Test data output (TDO),TDO is the serial output for test instructions and data from the test logic Changes in the state of the signal driven through TDO occurs on the falling edge of TCK. External logic sample TDO on the rising edge of TCK.,Test reset input (TRST),Optional Provides for asynchronous initialization of the TAP controller TMS should be held at 1 while the signal applied at TRST changes from 0 to 1. Undriven input produces a logical response identical to the application of a logic 1. (Pull-up resistor),Pull-up Registers For TAP Controller,Reset of JTAG,Test Access Port,TAP controller is controlled by 5 pins TMS TRST TCK,TAP FSM,Boundary-scan Register (1),Boundary-scan Register in Alter Devices (1),Boundary-scan Register in Alter Devices (2),Boundary-scan Register Cell of Altera MAX7000 (IO),Boundary-scan Register Cell of Altera MAX7000 (IN),TAP FSM,Timing of Actions in a Controller State,Waveform for Instruction Scan,Waveform for Data Scan,TEST_LOGIC/RESET State,The BST circuitry is disabled The device is in normal operation The instruction register is initialized. Initial instruction is IDCODE or BYPASS (if IDCODE is not supported). Enter TEST_LOGIC/RESET Mode device power-up Can be forced to the TEST_LOGIC/RESET state by holding TMS high for five TCK clock cycles holding the TRST pin low (if the optional TRST pin is supported.),How to reach SHIFT_IR state?,SHIFT_IR state,Shift in the instruction code into “instruction register” TDO pin It is activated at the first falling edge of TCK after entering shift states and is tri-stated at the first falling edge of TCK after leaving shift states. When shift data in SHIFT_IR state, the initial state of the instruction register is shifted out on the falling edge of TCK while new instruction is shifted in from TDI pin TDI pin Instruction code is entered by shifting data on the TDI pin on the rising edge of TCK The last bit of the opcode must be clocked at the same time that the next state, EXIT1_IR, is activated The circuits exit “SHIFT_IR” state by entering EXIT1_IR state,EXIT1_IR State,EXIT1_IR is entered at the end