Verilog 分频器设计module adder(clk,z);output z;reg q;reg z;always(posedge clk)beginif(q%9=0)z 1; (N/2)(N-1) - 0always (posedge i_clk, negedge rst_n)beginif (!rst_n) o_clk 1) - 1; (N1)+1)(N-1) - 0always (posedge i_clk or negedge rst_n)beginif (!rst_n)clk_p 1) / 0 (N1)clk_p 1) - 1; (N1)+1)(N-1) - 0always (negedge i_clk or negedge rst_n)beginif (!rst_n)clk_n 1) / 0 (N1)clk_n = 1;elseclk_n = 0;endendendmodule仿真波用 Verilog 设计一个 5 分频器默认分类 2009-06-12 08:29:25 阅读 127 评论 0 字号：大中小 订阅 .用 Verilog 设计一个 5 分频器。5 分频，奇数分频都可以类似这么做,只需要改 div1 和 div2 的参数。div1 为奇数分频除 2 的余数。采用上升延和下降延分别触发不同波形，最后叠加的方式产生奇数分频。module divfreq(clk, clk1x, rst, clk1xpose, clk1xnege, coutpose, coutnege);input clk;input rst;output clk1x;output clk1xpose;output clk1xnege;output2:0 coutpose;output2:0 coutnege;reg clk1xpose;reg clk1xnege;reg2:0 coutpose;reg2:0 coutnege;parameter div1 = 1 , div2 = 4; / div1 5 / 2, div2 = 5 - 1assign clk1x = clk1xpose | clk1xnege;always(posedge clk or negedge rst)beginif(!rst)clk1xpose = 0; else if(coutpose = div1)clk1xpose = clk1xpose;else if(coutpose = div2)clk1xpose = clk1xpose;else clk1xpose = clk1xpose;endalways(negedge clk or negedge rst)beginif(!rst)clk1xnege = 0;else if(coutnege = div1)clk1xnege = clk1xnege;else if(coutnege = div2)clk1xnege = clk1xnege;else clk1xnege = clk1xnege;endalways(posedge clk or negedge rst)beginif(!rst)coutpose = 0;else if(coutpose = div2)coutpose = 0;elsecoutpose = coutpose + 1;endalways(negedge clk or negedge rst)beginif(!rst)coutnege = 0;else if(coutnege = div2)coutnege = 0;elsecoutnege = coutnege + 1;endendmodule