乐曲硬件演奏电路的 EDA 设计- I -摘 要可编程逻辑器件（简称 PLD）是一种由用户编程来实现某种逻辑功能的新型逻辑器件，主要包括 FPGA 和 CPLD 两大类。FPGA 和 CPLD 分别是现场可编程门阵列和复杂可编程逻辑器件的简称。FPGA/CPLD 最明显的特点是高集成度、高速度和高可靠性，其时钟延时可小至纳秒级，集合器并行工作方式，在超高速应用领域和实时测控方面有着非常广阔的应用前景。在高可靠领域，如果设计的得当，将不会存在类似于 MCU 的复位不可靠和 PC 的可能跑飞等问题。FPGA/CPLD 的高可靠性还表现在几乎可将整个系统下载于同一芯片中，实现所谓的片上系统，从而大大的缩小的体积，易于管理和屏蔽。硬件的乐曲演奏电路是用 FPGA 将 50M 时钟进行分频，两路的分频分别产生节拍和音调。随着时间的推移节拍计数信号会记录当前在乐谱中的位置，根据当前的位置会将音调控制的信号数组置成乐谱上的音调，挂载信号数组上面的音调发生器会产生相应的音调，其中为增加音乐的效果信号数组上挂载了一个 8 个 LED 控制器，不同的音调灯的亮灭的组合会各不同会产生看似随机的等组合实际灯亮的组合根据音调的确定是固定的。此现场可编程门阵列的程序是演奏生日快乐的乐曲的。下面会有他的乐谱。关键词 FPGA，CPLD, 乐曲演奏电路，音乐节拍发生器，音乐译码电路，可编程逻辑器件分频器。 沈阳工程学院课程设计（论文）- II -AbstractProgrammable logic devices (hereinafter referred to as PLD) is a kind of programming by the user to achieve a certain logic function of the new logic devices, including two kinds of FPGA and CPLD. FPGA and CPLD were field programmable gate array and complex programmable logic device referred to as. FPGA/CPLD the most obvious characteristic is high integration, high speed and high reliability, the clock time delay can be small to nanosecond level, collector parallel work way, in the ultra high speed applications and real-time measurement and control aspects has a very broad application prospects. In the field of high reliability, if the design is proper, there will not be similar to the MCU reset is not reliable and PC can be run problems such as fly. FPGA/CPLD high reliability as well as in almost the whole system can be download from the same chip, so as to realize the so-called chip system, thus greatly reduced volume, easy to management and shielding. The music of hardware circuit is playing with FPGA will fifty m clock for crossover, two-way crossover respectively produce rhythm and tone. With the passage of time beat count signal will record the current position of the music, according to the current position will tone control signal array set to music on the tones, mount signal array the tone generator can produce corresponding tones, the music to increase the effect of array signal on mount a eight LED controller, different tones lamp light out of the different combination will can produce a seemingly random combined the actual combination of light according to determine the tone is fixed. The field programmable gate array program is playing the music of happy birthday. Below will have his music.Keywords FPGA, FPGA, CPLD, music performance, music beat generator circuit, music decoding circuit, programmable logic devices frequency divider.乐曲硬件演奏电路的 EDA 设计- III -目 录摘 要 .IABSTRACT .II1 引言 .11.1 EDA 技术的发展 .11.2 硬件描述语言的产生 .11.3 VHDL 语言特点 .11.4 EDA 的发展趋势 .12 乐曲演奏系统设计原理分析 .32.1 乐曲演奏基本要求 .32.2 乐曲演奏原理 .33 系统硬件设计 .63.1 现场可编程门阵列（FPGA） .63.1.1 FPGA 的基本结构 .63.1.2 Altera 公司的 FPGA.63.2 FLEX 系列的结构特点 .73.2.1 概述 .73.2.1 FLEX 的特点 .74 乐曲硬件演奏电路的 VHDL 实现 .84.1 音乐节拍的生成 .