1、要求：设计一个四位二进制计数器，将计数结果 由数码管显示，显示结果为十进制数。数码管选通为 低电平有效，段码为高电平有效。 分析：VHDL 描述包含五部分：计数器、将四位二进 制数拆分成十进制数的个位和十位、二选一的数据选 择器、七段译码、数码管选通控制信号上图中六部分对应六条并发描述语句，他们之间的连 线定义为信号library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter3 isPort ( clk:in STD_LOGIC; clk1 : in STD_LOGIC;clr : in STD_LOGIC;en : in STD_LOGIC;co : out STD_LOGIC;scanout:out std_logic_vector(1 downto 0);ledout:out std_logic_vector(6 downto 0); end counter3;architecture Behavioral of counter3 is signal cnt:std_logic_vector(3 downto 0); signal cnt1:std_logic_vector(3 downto 0); signal cnt2:std_logic_vector(3 downto 0); signal hex:std_logic_vector(3 downto 0); signal scan:std_logic_vector(1 downto 0);四位二进制计数器 四位二进制数拆分 二选一的数据选择器 七 段译码 数码管选通控制信号产生 clk en clr Clk1 cnt Cnt1 Cnt2 hex ledout scanout scan NOT LED signal led:std_logic_vector(6 downto 0); begin -四位二进制计数器四位二进制计数器 process(clk) begin if clkevent and clk=1 then if clr=1 then cnt0); co=“10“ then scan0); co=“10“ then scan=“01“;else scan=scan+1;end if;end if; end process; scanout=scan; with scan select hex=cnt(3 downto 0) when “01“,cnt(7 downto 4) when others; ledout=not led; with hex select led=“1111001“ when “0001“, “0100100“ when “0010“, “0110000“ when “0011“, “0011001“ when “0100“, “0010010“ when “0101“, “0000010“ when “0110“, “1111000“ when “0111“, “0000000“ when “1000“, “0010000“ when “1001“, “0001000“ when “1010“, “0000011“ when “1011“, “1000110“ when “1100“, “0100001“ when “1101“,“0000110“ when “1110“, “0001110“ when “1111“, “1000000“ when others; end Behavioral;