U A HU A HU A HCPE/EE 421 MicrocomputersWEEK #102U A HU A HU A HInterpreting the Timing DiagramThe 68000 Read CycleAlan Clements3U A HU A HU A HActual behavior of a D flip-flopTiming Diagram of a Simple Flip-Flop Idealized form of the timing diagramData hold timeData setup timeMax time for output to become valid after clockAlan Clements4U A HU A HU A HAn alternative form of the timing diagramGeneral form of the timing diagramAlan Clements5U A HU A HU A HThe Clock A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7Alan Clements6U A HU A HU A HA memory access begins in clock state S0 and ends in state S7Alan Clements7U A HU A HU A HThe most important parameter of the clock is the duration of a cycle, tCYC. Alan Clements8U A HU A HU A HAt the start of a memory access the CPU sends the address of the location it wishes to read to the memoryAlan Clements9U A HU A HU A HAddress Timing We are interested in when the 68000 generates a new address for use in the current memory access The next slide shows the relationship between the new address and the state of the 68000s clockAlan Clements10U A HU A HU A HInitially, in state S0 the address bus contains the old addressIn state S1 a new address becomes valid for the remainder of the memory accessAlan Clements11U A HU A HU A HThe time at which the contents of the address bus change can be related to the edges of the clock.Alan Clements12U A HU A HU A HAddress Timing Lets look at the sequence of events that govern the timing of the address bus The “old” address is removed in state S0 The address bus is floated for a short time, and the CPU puts out a new address in state S1Alan Clements13U A HU A HU A HThe old address is removed in clock state S0 and the address bus floatedAlan Clements14U A HU A HU A HtCLAVThe designer is interested in the point at which the address first becomes valid. This point is tCLAVseconds after the falling edge of S0.Alan Clements15U A HU A HU A HThe memory needs to know when the address from the CPU is valid. An address strobe, AS*, is asserted to indicate that the address is valid.Alan Clements16U A HU A HU A HAddress and Address Strobe We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted When AS* is active-low it indicates that the address is valid We now look at the timing of the clock, the address, and the address strobeAlan Clements17U A HU A HU A HAS* goes active low after the address has become validAS* goes inactive high before the address changesAlan Clements18U A HU A HU A HAS* goes low in clock state S2Alan Clements19U A HU A HU A HThe Data Strobes The 68000 has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access To keep things simple, we will use a single data strobe, DS* The timing of DS* in a read cycle is the same as the address strobe, AS* Alan Clements20U A HU A HU A HThe data strobe, is asserted at the same time as AS* in a read cycleAlan Clements21U A HU A HU A HThe Data Bus During a read cycle the memory provides the CPU with data The next slide shows the data bus and the timing of the data signal Note that valid data does not appear on the data bus until near the end of the read cycleAlan Clements22U A HU A HU A HData from the memory appears near the end of the read cycleAlan Clements23U A HU A HU A HAnalyzing the Timing Diagram We are going to redraw the timing diagram to remove clutter We arent interested in the signal paths themselves, only in the relationship between the signalsAlan Clements24U A HU A HU A HWe are interested in the relationship between the clock, AS*/DS* and the data in a read cycleAlan Clements25U A HU A HU A HThe earliest time at which the memory can begin to access data is measured from the point at which the address is first validAlan Clements26U A HU A HU A HAddress becomes validData becomes validThe time between address valid and data valid is the memorys access time, taccAlan Clements27U A HU A HU A HCalculating the Access Time We need to calculate the memorys access time By knowing the access time, we can use the appropriate memory component Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular systemAlan Clements28U A HU A HU A HData from the memory is latched into the 68000 by the falling edge of the clock in state S6.Alan Clements29U A HU A HU A HData must be valid tDICLseconds before the falling edge of S6Alan Clements30U A HU A HU A HWe know that the time between the addr