A Module Generator for High Speed CMOS Current Output Digital/Analog ConvertersRobert R. Neff, Paul R. Gray, and Alberto Sangiovanni-VincentelliElectrical Engineering and Computer Sciences University of California, BerkeleyAbstractThis paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close cou- pling of optimization and layout allows accurate incorpora- tion of layout parasitics in optimization. Prototypes have been demonstrated for an 8-bit, 100-MHz specification, driving a37.5-ohm video load, and a static 10-bit specification, driving a 4mA full-scale output current. Both designs use a 5-V supply in a standard 1.2 m CMOS process.1I. IntroductionIn mixed-signal integrated circuits, the analog part of the design often occupies a small portion of the physical die area but requires a disproportionately large amount of the design effort and time. One approach for reducing design time is to develop module generators for frequently occurring analog circuit functions, synthesizing blocks that are competitive with manual design in performance and die area (1). One fre- quently occurring function is the digital-analog converter (DAC). These range in requirements from low-speed, high- accuracy circuits, usually implemented with oversampled approaches, to relatively high speed, low to medium resolu- tion applications, usually implemented with current-switched or resistor string DACs. This paper describes a methodology for low level module generation and its application to high- speed current switched DAC modules in a CMOS technology. By changing technology or specification inputs, new designs may be created in a few hours. This methodology is adaptable to other DAC and circuit architectures.Generation of mixed-signal analog blocks can be approached in several ways. In the top-down, hierarchical approach con- straint values are passed down through layers of the design, with the bottom layer corresponding to the transistors. This approach was used in an earlier paper (2) with the current- switched DAC used as an example. The hierarchical approach is very useful at higher system levels, but near the transistorlevel a flat optimization approach may offer advantages.When1. This research was supported by SRC grant 94-DC-324.an optimal design is desired, a flat approach is better able to optimize all variables simultaneously. When a complex cir-cuit behavior is difficult to separate and evaluate in a hierar-chically, a flat approach is the only option.In this paper, a single-level optimization is applied to the current-switched DAC function, allowing simultaneous optimization of architecture and device level design vari- ables, and easy incorporation of all aspects of performance, including layout related parasitics when predicting static and dynamic performance. For layout synthesis a stretching and tiling approach is used, enabling accurate performance pre- diction and rapid design implementation.II. Module Generation Methodology.Fig. 1 illustrates the module generation methodology. Input data is separated into information classes, which are used during the optimization step to find the best set of design variables. The design variables are then passed to the layout program, creating the DAC module. Design optimization can be further decomposed into two parts, the optimization algorithm and the design estimation process.Figure 1. Module Generation MethodologyMOSFET model Matching = f(w,l)TopologyCircuit Synthesis:DAC LayoutDAC SpecsLayout TemplatesOptimized DesignDAC ModuleSpiceOptim it requires less than 5 minutes to complete.III. DAC ArchitectureThe DAC architecture is a current output structure, using PMOS devices to source current. This is compatible with video DAC application requirements, and the architecture may also be used with an I/V converter to create a voltage out- put. The architecture uses a two dimensional array of current sources (8), with a local row / column digital decode, which allows individual selection of each cell. The segment cells in the main section of the DAC are M lsb in value, and a section of lsb segments is placed across the top of the array. Digital information is routed in from the top and the sides of the array, and analog signals are passed through a central vertical bus, minimizing capacitive coupling between digital and analog signals. Where digital column signals must cross over analog signals they are shielded. Rows and columns are selected in an order which minimizes gradient effects from both process and supply drop gradients (9). Additionally, the right and left halves of the rows are selected in a complementary way, to reduce vertical gradient effects. Bias cells are placed in the c