Chap1. Fundamentals.1Fundamentals on Testing and Design for TestabilityChap1. Fundamentals.2Design Verification, Testing and Diagnosis Design Verification: Ascertain the design perform its specified behavior Testing: Exercise the system and analyze the response to ascertain whether it behaves correctly Diagnosis: To locate the cause of misbehavior after the incorrect behavior is detectedChap1. Fundamentals.3Some Real Defects in Chips Processing Faults missing contact windows parasitic transistors oxide breakdown Material Defects bulk defects (cracks, crystal imperfections) surface impurities (ion migration) Time-Dependent Failures dielectric breakdown electromigration Packaging Failures contact degradation seal leaksChap1. Fundamentals.4Faults, Errors and Failures Fault: A physical defect within a circuit or a system May or may not cause a system failure Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states Caused by faults Failure: Deviation of a circuit or system from its specified behavior Fails to do what it should do Caused by an error Fault - Error - Failure Chap1. Fundamentals.5Scenario for Manufacture TestTEST VECTORSMANUFACTURED CIRCUITCOMPARATORCIRCUIT RESPONSEPASS/FAILCORRECT RESPONSESChap1. Fundamentals.6Purpose of Manufacture Testing Verify Manufacture of Circuit Improve System Reliability Diminish System Cost Cost of repair goes up by an order of magnitude each step away from fab line0.5550500IC TestBoard TestSystem TestWarranty Repair1011001000Cost per fault (Dollars)B. Davis, The Economics of Automatic Testing, McGRAW-HILL, 1982.Chap1. Fundamentals.7Testing and QualityASIC FabricationTestingYield: Fraction of good parts RejectsShipped PartsQuality: Defective parts per million (DPM)* Quality of shipped part is a function of yield Y and the test (fault) coverage T.Chap1. Fundamentals.8Fault Coverage* Fault coverage T is the measure of the ability of a set of tests to detect a given class of faults that may occur on the device under test.T =# of detected faults # of possible faultsChap1. Fundamentals.9Defect Level* Defect Level, DL is the fraction of the shipped parts that are defective.DL = 1 - Y(1-T)Y: yield T: fault coverageChap1. Fundamentals.10Relating Defect Level to Fault Coverage01020304050607080901000.1.2.3.4.5.6.7.8.91Y=.99Y=.90Y=.75Y=.50Y=.25Y=.10Y=.01Y = YieldFault Coverage, T (%)DL = 1 - Y(1-T)Chap1. Fundamentals.11Defect Level, Yield and Fault Coverage50%90%67,000 75%90%28,000 90%90%10,000 95%90%5,000 99%90%1,00090%90%10,000 90%95%5,000 90%99%1,000 90%99.9%100YieldFault CoverageDPMChap1. Fundamentals.12ASIC What is ASIC: Application Specific Integrated Circuits Why we need ASICs Microelectronic economics Volume Time to market QualityChap1. Fundamentals.13ASICs Demand* While ASIC density and complexity haveexploded, global market pressures haveincreased the demand for both QualityQualityand Quick TurnaroundQuick Turnaround.Chap1. Fundamentals.14Test Development Time vs. TestabilityControllability and observability as a percentage of circuit coveredMeasured development times Extrapolated curve403530252015105020406080100Chap1. Fundamentals.15Time-to-Market ModelLost revenue due to delayTimeGrowthStagnationDeclineDelay in reaching market* 1/81/8delay of the productlifetime reduces 1/31/3revenue.Chap1. Fundamentals.16Why Testing is Difficult ? Test application time can be exploded for exhaustive testing of VLSI For a combinational circuit with 50 inputs, we need 250= 1.126x1015test patterns. Assume one test per 10-7sec, it takes 1.125x108sec = 3.57yrs. to test such a circuit. Test generation of sequential circuits are even more difficult. Lack of Controllability and Observability of Flip-Flops (Latches) Functional testing may not be able to detect the physical faults Chap1. Fundamentals.17How To Do Test Fault Modeling Identify target faults Limit the scope of test generation Make analysis possible Test Generation Automatical or Manual Fault Simulation Assess completeness of tests Testability Analysis Analyze a circuit for potential problem on test generation Design For Testability Design a circuit for guaranteed test generation Introduce both area overhead and performance degradationChap1. Fundamentals.18The New Challenges for VLSI Testing Chip, Board, Module otherwise, f is an undetectable fault For an undetectable fault f No test can simultaneously activate f and create a sensitized path to a primary outputzfx( )= z x( )Chap1. Fundamentals.68Undetectable Fault G1output stuck-at-0 fault is undetectable Undetectable faults do not change the function of the circuit The related circuit can be deleted to simplify the circuit xs-a-0abczG1Chap1. Fundamentals.69Test Set Complete detection test set: A set of tests that detect any detectable faults in a class of faults The quality of a test set is measured b