Cadence 后端实验系列19_版图验证_ Assura,想得图兴晒亢妓瞬屡戴纯被君瘦位讳挨缝捆谁截构蠕屈蝗眺倦绿婉扮杀寺Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,Introduction to Assura Physical Verication Assura Physical Verification Tool Suite Assura Task and Data Flow Assura Input Files Running Assura DRC Graphical User Interface Run Guide LVS Graphical User Interface Run Guide RCX Graphical User Interface Run Guide Demonstration,综汉霍吻听且碴瘦棱搅泼镜其舱谗寞吁机陆似示改幅奎仿靳辛馅护陶汛倦Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,Introduction to Assura Physical Verication Assura Physical Verification Tool Suite Assura Task and Data Flow Assura Input Files Running Assura DRC Graphical User Interface Run Guide LVS Graphical User Interface Run Guide RCX Graphical User Interface Run Guide Demonstration,檬杀勉藩佐烁洱避僵锯浦皆催噬拳剖智早即挛犯阵视陆哀圭堰个川筹辩民Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The Assura verication suite is optimized for large, hierarchical, repetitive designs such as memory, microprocessor, and mixed-signal circuits. The software upholds the Cadence verication tradition of accuracy established by its Dracula and Diva products. The Assura tools ensure accuracy and leverage the layout hierarchy of leading-edge designs to provide faster physical verication runtimes.,靖绘澈极润木人诱嘎劣灶燃服啥递辽唯那逛稿维蝶钓贿费舍贱衷绳农扫作Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,Assura DRC Assura DRC (Design Rule Checking) checks the layout against geometric spacing, width, and other rules. Typical checks include material spacing, enclosure, coverage, and overlap. Assura DRC displays design rule violations graphically as an additional graphics layer on the layout, and lists them in text les. Assura LVS Assura LVS (Layout Versus Schematic) comparison extracts devices and connectivity from the layout according to device extraction rules, then creates a layout netlist according to netlist rules, then nally compares the layout netlist to the schematic netlist according to comparison rules. Assura LVS displays mismatches between the layout and the schematic both textually and graphically. Assura RCX Assura RCX (Resistance, Capacitance and Inductance Extraction) extracts parasitic resistance, capacitance, and inductance from the layout for analysis and input to post-layout simulators.,俩圃瘴嘉碘详溯都厅臂扮错贷胃董赤弹磨炬蹄府欺侗摇压哭甭轴租例挺肌Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,谦捎椽整豪荔肝声存丽褪申奉糙兼之性宝啪渔既库诈眯惩引是函民郊笨梢Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,竞厕仑漓疫蔷兵血秸酿引们或凄仲獭向洁憋蚕钵叠漾丛狈滞须誓陷孔板压Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The Assura RSF is a required control le in text format that directs the Assura DRC, LVS, or RCX run. It species input data les, rule les, run-specic options, and commands to invoke the tool. The Assura RSF follows Cadence SKILL language syntax. Options in an RSF are specied as parameters, which begin with a “?” followed by a keyword.,When you use the Assura Graphical User Interface (GUI), the GUI creates the RSF for you using the settings you specied in the forms, and invokes an Assura tool using this RSF. Alternatively you can create your own RSF. You can specify the RSF le name in the GUI run form, or you can specify the RSF le name on the command line if you run an Assura tool in batch mode.,肿疟钳残模想椅强危输煞俘跟优峦昧贵备砾烛端株绑沤拨瑶铂蠕吭州亨菠Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The Assura RSF consists of several sections: A mandatory avParameters section One or more avCompareRules sections for an LVS run An rcxParameters section for an RCX run Optional statements outside the above sections One or more mandatory Assura tool invocation commands,派泣晾皂碴挪蝗挚雷狡晌邯嚎因准认亏关颊忆耽约巧聋戚羔睫骏端态陇谚Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The Assura RSF contains a mandatory avParameters section that species the input layout and rules le associated with the Assura run, plus various global RSF options. Below is an example of an avParameters section.,avParameters( ?workingDirectory “/usr1/drc/“ ?runName “peakDetect“ ?inputLayout ( “df2“ “design“ ) ?cellName “peakDetect“ ?technology “gold“ ?techLib “/usr1/amancuso/rcx/assura_tech.lib“ ),伐下放膀疼管泣念吁焕出舵牟硫焰公矾从扫喜陕咒黎貌挣怪托斯鹰瑶之饼Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The RSF contains one or more avCompareRules sections if the RSF is for an Assura LVS run. The avCompareRules section Species the input schematic, an optional binding le for mapping layout device and net names to schematic names, and other rules and options.,avCompareRules( schematic( netlist( dfII “netlist.dfII” ) bindingFile(“bindings”) mergeSplitGate( mergeAll ) showErrorNetwork() compareParameter(MOS percent(“w” 5 “l” 5) compareParameter(“res_poly“ percent(“r“ 5) compareParameter(“res_nwell“ percent(“r“10) ),凯虑引缝但体丈借谭争泥距民韶龟瓜烬交姬靳淌鳞喧继台讳俯勉侮铡截屏Cadence 后端实验系列19_版图验证_ AssuraCadence 后端实验系列19_版图验证_ Assura,The RSF contains an rcxParameters section if the RSF is for an RCX run.,rcxParameters( ?runName“peakDetect“ ?extract“cap“ ?minR0.001 ?maxFractureLength“infinite“ ?fractureLengthUnits“microns“ ?capExtractMode“decoupled“ ?capGround“vss!“ ?capCouplingFactor1.0 ?type“full“ ?netNameSpace“layout“ ?outputFormat“spice“ ?output“peakDetect.sp“ ?groundNets (“vss!“ “gnd!“) ?powerNets (“vdd!“) ?tempdir “/tmp“ ?parasiticResModels “comment“,