高性能VLSI设计,任课老师 周电 中科院半导体所 徐渊,Outline,Introduction to VLSI design From application to specification Architecture synthesis Verification and testing scheme Performance-driven physical design CAD tools Topics on SOC,Chapter1:Introduction to VLSI design,History and the road map Traditional design flow,Section1:History and the road map,The history of IC The invention of transistor The invention of integrated circuit IC has changed our life Moores Law IC performance and complexity have been doubled in every two years Road Map,The history of IC,Bipolar1947: Transistor( Bardeen/Bell Lab) 1949 : Bipolar Transistor 1962-1972 :TTL ,ECL I2L MOS 1970 NMOS PMOS CMOS 1963 -?,Moores Law,In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980s. 2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) - 2001 140 Million transistor (HP PA-8500),Technology Trend (roadmap),International Technology Roadmap for Semiconductors (ITRS),Section2: Traditional design flow,Traditional design flow (see slides design-flow) What has not been addressed in depth Understand application Architecture synthesis Verification is not complete,Chapter2: From application to specification,An FIR filter application The mathematical description implementation restrictions Speed and power IO Protocol Processing technology and ,Algorithm of MSDAP,Power Of Two，POTExample：,Algorithm of MSDAP FIR,How to realize shifter：,I/O,Input：Reset，Data_Clk，Sys_Clk ，Data_in，Data_in_read， Co_effi，Co_effi_start EEPROM_enOutput：Data_out，Data_out_ready,Behavior architecture,Simulation Waveform,Final Architecture,Chapter3 Architecture Synthesis,Timing Power Silicon size Automation Example (see slides fast),FIR Filter Architecture,Finite Impulse Response filters all have the same transfer function:y(n) = for filter of length L, indexes m and n and coefficients h. This formula does not specify an architecture. Vastly different architectures can all be mathematically correct. Mathematically correct does not mean satisfactory from an engineering standpoint.,Finite Impulse Response filters all have the same transfer function:y(n) = for filter of length L, indexes m and n and coefficients h. This formula does not specify an architecture. Vastly different architectures can all be mathematically correct. Mathematically correct does not mean satisfactory from an engineering standpoint.,FIR Filter Architecture,Register,Register,Register,Register,X,X,X,X,Data In,Data Out,Coefficients,Traversal,Symmetric Coefficient Sets,Positive Even Symmetry C0 = 0.12345 C1 = -0.0054321 C2 = -0.0054321 C3 = 0.12345,Negative Odd Symmetry C0 = 0.12345 C1 = -0.0054321 C2 = 0.01987 C3 = 0.0054321 C4 = -0.12345,Symmetry can be odd or even, positive or negative,Coefficient Symmetry,Coefficient sets are frequently symmetrical, as this gives linear phase response. Coefficients have positive symmetry if, for a system of L coefficients and 0 n L/2, Cn = CL-n-1. If L mod 2 = 1, the system has odd symmetry and the middle coefficient may not match any other coefficient. Symmetry is negative if Cn = -CL-n-1. Symmetric factoring can reduce the number of arithmetic operations in a filter function. This is just an application of arithmetic factoring: a*c + b*c = (a + b)*c,Symmetric Traversal,X,X,X,X,Data In,Reg.,+,+,Reg.,Reg.,Reg.,+,Data Out,Transpose Format,Transpose format has built in pipelining, at the cost of larger operators and storage elements.,C3,C2,C0,C1,t0: Reg 0 = x, Reg1 = x, Reg2 = x, Reg3 = x t1: Reg0 = D0 * C3, Reg1 = x, Reg2 = x, Reg3 = x t2: Reg0 = D1 * C3, Reg1 = D1 * C2 + D0 * C3, Reg2 = x, Reg3 = x t3: Reg0 = D2 * C3, Reg1 = D2 * C2 + D1 * C3, Reg2 = D2 * C1 + D1 * C2 + D0 * C3, Reg3 = x t4: Reg0 = D3 * C3, Reg1 = D3 * C2 + D2 * C3, Reg2 = D3 * C1 + D2 * C2 + D1 * C3, Reg3 = D3 * C0 + D2 * C1 + D1 * C2 + D0 * C3After N cycles, the Nth register has accumulated the sum of products.,Transpose Data Flow,Symmetric Transpose,X,X,Data In,Reg.,+,+,Reg.,Reg.,Reg.,+,C0,C1,Data Out,Filter templates shown have been very short: 4 or 8 taps. In practice, such a short filter does not do much filtering. In the following examples, all filters were specified were for a rejection ration of 60 db, a passband of 9.6 kHz and a stopband of 12 kHz.,Area Considerations,All the design templates shown so far process one data sample every clock cycle. This means there is no operator reuse. Scheduling multiple operations per operator can save an order of magnitude in area. In the limit, all operations are done by a single adder. Devices with any degree of parallelism/reuse can be built.,Data RAM,+,Accumulator,State Machine,Output Register,Data Out,Processor Style,Data In,