lClock Buffer Basics Clocks are the basic building blocks for all electronics today. For every data transition in a synchronous digital system, there is a clock that controls a register. Most systems use Crystals, Frequency Timing Generators (FTGs), or inexpensive ceramic resonators to generate precision clocks for their synchronous systems. Additionally, clock buffers are used to create multiple copies, multiply and divide clock frequencies, and even move clock edges forwards or backward in time. Many clock-buffering solutions have been created over the past few years to address the many challenges required by todays high-speed logic systems. Some of these challenges include: High operating and output frequencies, propagation delays from input to output, output to output skew between pins, cycle-tocycle and long-term jitter, spread spectrum, output drive strength, I/O voltage standards, and redundancy. Because clocks are the fastest signals in a system and are usually under the heaviest loads, special consideration must be given when creating clocking trees. In this chapter, we outline the basic functions of non-PLL and PLL-based buffers and show how these devices can be used to address the high-speed logic design challenges.In todays typical synchronous designs, multiple clock signals are often needed to drive a variety of components. To create the required number of copies, a clock tree is constructed. The tree begins with a clock source such as an oscillator or an external signal and drives one or more buffers. The number of buffers is typically dependent on the number and placement of the target devices. In years past, generic logic components were used as clock buffers. These were adequate at the time, but they did little to maintain the signal integrity of the clock. In fact, they actually were a detriment to the circuit. As clock trees increased in speed and timing margins reduced, propagation delay and output skew became increasingly important. In the next several sections, we discuss the older devices and why they are inadequate to meet the needs of todays designs. The definitions of the common terms associated with modern buffers follow. Finally, we address the attributes of the modern clock buffer with and without a PLL. The FTG that is often used as a clock source is a special type of PLL clock buffer.Early BuffersA clock buffer is a device in which the output waveform follows the input waveform. The input signal propagates through the device and is re-driven by the output buffers. Hence, such devices have a propagation delay associated with them. In laddition, due to differences between the propagation delay through the device on each input-output path, skew will exist between the outputs. An example of a non-PLL based clock buffer is the 74F244 that is available from several manufacturers. These devices have been available for many years and were suitable for designs where frequencies were below 20 MHz. Designers would bring in a clock and fan it out to multiple synchronous devices on a circuit card. With these slow frequencies and associated rise times, designers had suitable margins with which to meet setup and hold times for their synchronous interfaces. However, these buffers are not optimal for todays high-speed clocking requirements. The 74F244 suffers from a long propagation delay (3 to 5 ns) and long output-to-output skew delays. Non-PLL based clock buffers have improved in recent years and use more advanced I/O design techniques to improve the output-to-output skew. As the clock period gets shorter, the uncertainty or skew in the clock distribution system becomes more of a factor. Since clocks are used to drive the processors and to synchronize the transfer of data between system components, the clock distribution system is an essential part of the system design. A clock distribution system design that does not take skew into consideration may result in a system with degraded performance and reliability.Clock SkewSkew is the variation in the arrival time of two signals specified to occur at the same time. Skew is composed of the output skew of the driving device and variation in the board delays caused by the layout variation of the board traces. Since the clock signal drives many components of the system, and since all of these components should receive their clock signal at precisely the same time in order to be synchronized, any variation in the arrival of the clock signal at its destination will directly impact system performance. Skew directly affects system margins by altering the arrival of a clock edge. Because elements in a synchronized system require clock signals to arrive at the same time, clock skew reduces the cycle time within which information can be passed from one device to the next.As system speeds increase, clock skew becomes an increasingly large portion of the total cycle time. When cycle times were 50 ns, clock skew was rarely a design priority. Even if s