CSE477 VLSI Digital Circuits Fall 2003 Lecture 08: MOS & Wire Capacitances,Mary Jane Irwin ( www.cse.psu.edu/mji ) www.cse.psu.edu/cg477 Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic,Review: Delay Definitions,t,Vout,Vin,input waveform,output waveform,t,signal slopes,Vin,Vout,CMOS Inverter: Dynamic,VDD,Rn,Vout = 0,Vin = V DD,CL,tpHL = f(Rn, CL),Transient, or dynamic, response determines the maximum speed at which a device can be operated.,Sources of Capacitance,Cw,wiring (interconnect) capacitance,intrinsic MOS transistor capacitances,Vout2,Vin,extrinsic MOS transistor (fanout) capacitances,Vout,CL,ndrain,pdrain,Intrinsic MOS Capacitances,Structure capacitances Channel capacitances Diffusion capacitances from the depletion regions of the reverse-biased pn-junctions,CGS,CSB,CDB,CGD,CGB,S,G,B,D,CGS = CGCS + CGSO,CGD = CGCD + CGDO,CGB = CGCB,CSB = CSdiff,CDB = CDdiff,MOS Structure Capacitances,xd,Source n+,Drain n+,W,Ldrawn,xd,Poly Gate,n+,tox,Leff,Top view,lateral diffusion,MOS Channel Capacitances,S,D,p substrate,B,G,n+,CGS = CGCS + CGSO,CGD = CGCD + CGDO,CGB = CGCB,The gate-to-channel capacitance depends upon the operating region and the terminal voltages,Review: Summary of MOS Operating Regions,Cutoff (really subthreshold) VGS VT Exponential in VGS with linear VDS dependence ID = IS e (qVGS/nkT) (1 - e -(qVDS/kT) ) (1 - VDS) where n 1 Strong Inversion VGS VT Linear (Resistive) VDS VDSAT = VGS - VT ID = k W/L (VGS VT)VDS VDS2/2 (1+VDS) (VDS) Saturated (Constant Current) VDS VDSAT = VGS - VT IDSat = k W/L (VGS VT)VDSAT VDSAT2/2 (1+VDS) (VDS),Average Distribution of Channel Capacitance,Channel capacitance components are nonlinear and vary with operating voltage Most important regions are cutoff and saturation since that is where the device spends most of its time,MOS Diffusion Capacitances,S,D,p substrate,B,G,n+,CSB = CSdiff,CDB = CDdiff,The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pn-junctions.,Source Junction View,side walls,channel,W,xj,channel-stop implant (NA+),source bottom plate (ND),LS,substrate (NA),Cdiff = Cbp + Csw = Cj AREA + Cjsw PERIMETER = Cj LS W + Cjsw (2LS + W),junction depth,Review: Reverse Bias Diode,All diodes in MOS digital circuits are reverse biased; the dynamic response of the diode is determined by depletion-region charge or junction capacitance Cj = Cj0/(1 VD)/0)m where Cj0 is the capacitance under zero-bias conditions (a function of physical parameters), 0 is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient m = for an abrupt junction (transition from n to p-material is instantaneous) m = 1/3 for a linear (or graded) junction (transition is gradual) Nonlinear dependence (that decreases with increasing reverse bias),Reverse-Bias Diode Junction Capacitance,VD (V),Cj (fF),linear (m=1/3),abrupt (m=1/2),Cj0,Transistor Capacitance Values for 0.25,Example: For an NMOS with L = 0.24 m, W = 0.36 m, LD = LS = 0.625 m,CGC = Cox WL =,CGSO = CGDO = Cox xd W = Co W =,so Cgate_cap = CoxWL + 2CoW =,Cbp = Cj LS W =,Csw = Cjsw (2LS + W) =,so Cdiffusion_cap =,Transistor Capacitance Values for 0.25,Example: For an NMOS with L = 0.24 m, W = 0.36 m, LD = LS = 0.625 m,CGC = Cox WL = 0.52 fF,CGSO = CGDO = Cox xd W = Co W = 0.11 fF,so Cgate_cap = CoxWL + 2CoW = 0.74 fF,Cbp = Cj LS W = 0.45 fF,Csw = Cjsw (2LS + W) = 0.45 fF,so Cdiffusion_cap = 0.90 fF,Review: Sources of Capacitance,Vout,Cw,Vin,CGD12,M2,M1,M4,M3,Vout2,CG4,CG3,wiring (interconnect) capacitance,intrinsic MOS transistor capacitances,Vout2,Vin,extrinsic MOS transistor (fanout) capacitances,Vout,CL,ndrain,pdrain,Gate-Drain Capacitance: The Miller Effect,Miller Effect: A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value.,M1 and M2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).,Drain-Bulk Capacitance: Keqs (for 2.5 m),We can simplify the diffusion capacitance calculations even further by using a Keq to relate the linearized capacitor to the value of the junction capacitance under zero-bias Ceq = Keq Cj0,Extrinsic (Fan-Out) Capacitance,The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. Cfan-out = Cgate (NMOS) + Cgate (PMOS) = (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox) Simplification of the actual situation Assumes all the components of Cgate are between Vout and GND (or VDD) Assumes the channel capacitances of the loading gates are constant,