1,Chapter 8 Sequential Logic Design Practices （时序逻辑设计实践）,8.1 Sequential-Circuit Documentation Standards,General Requirements Logic Symbols State-Machine Descriptions word, state table, state diagram, transition list, etc. Timing Diagrams and Specifications,(了解,自学.),hold-time margin,Detailed timing diagram:,Functional timing diagram:,8.2 Latches and Flip-Flops,SSI Latches and Flip-Flops,74x74: two D flip-flops 74x109: two J-K flip-flops 74x375: four D latches,Switch Debouncing（开关消抖）,0,0,1,1,0,0,1,1,Use a bistable element for debouncing,存在”瞬时短路”的情况!,SDATA,Bus holder circuit（总线保持电路）,Multibit Registers and Latches,Multibit Latche：Multi-latches with a common enable input. Multibit Register：Multi-flip-flops with a common clock input.,(often used to store a collection of related bits),74x175: 4-bit register (有异步清零端，含低电平有效输出) 74x174: 6-bit register (有异步清零端，无低电平有效输出) 74x374: 8-bit register (含三态输出，OE_L为”输出使能”) 74x373: 8-bit latch (374的变种，电平有效) 74x273: 8-bit register (374的变种，不含三态输出，有清零端) 74x377: 8-bit register (374的变种，不含三态输出，有时钟使 能输入.),Commonly MSI Registers and Latches,4-bit register 74x175,6-bit register 74x174,three-state output,8-bit register 74x374,寄存器和锁存器的区别？ 寄存器374：边沿触发； 锁存器373：C有效期间，输出跟随输入变化。(电平有效),74x377 (clock enable),74x374 (output enable),74x377 (clock enable ),2-to-1 MUX,EN可用于屏蔽时钟有效沿,