Bridgeless PFC,Vivian sun,Bridgeless PFC,The purpose-For higher power range, the bridge power loss is high, especially at low line condition. For example, the bridge power loss of 1200W PS is about 24W. -The bridgeless PFC topology can reduce total power loss , improve efficiency and thermal performance.,Bridgeless PFC,The comparison of bridge and bridgeless PFCThe design process Power loss calculationDesign tools,The comparison of bridge and bridgeless PFC,Topology Power Loss and Parts Count Current Sensing Iac Sensing Floating Ground,The topology of bridge PFC,The Topology of Bridgeless PFC,Bridgeless PFC Operation,Comparison of Bridge and Bridgeless PFC,Current Sensing,Current Sensing,Current Sensing,Iac Sensing (bridge),Iac Sensing (bridgeless),The Floating Ground of Bridgeless PFC,With a coupled choke as boost inductor, no capacitor can link L and N to power GND, otherwise the choke will be shortened. So the power GND is floating with the switches on and off at a switching frequency.,The Comparison of Efficiency,Design Specifications,Vin=90264VAC Vo=380VDC Po=1200W Fs=100kHz PF0.98(Full load & high line) Eff92%,Block Diagram,Boost Inductor Design,Peak input current at low line Ipk:Duty cycle at low line D:,Boost Inductor Design,Boost inductance L:Delta I is 20% peak currentSelect L=300uH (initial inductance),Boost Inductor Design,Magnetic core: Arnold MS-185060-2 or Dongbu S184-086A Magnetic material : sendust (kool Mu)Al=86mH/1000T, Bs=0.95TWe choose: N=60According design tools, the maximum magnetic force is 120 Oersteds and the flux density is 0.56T(2/3)Bs.,Power Stage Design,Output capacitor selection (holdup time 20ms)Select C out =660uF (two 330uF/450V capacitor in parallel) Main switch selectionTwo STW26NM60 (600V/30A) in parallel Boost diode selectionLow reverse current and fast reverse recovery diode shall be selected. SDT12S06 or STTH1506TTI is preferred.,Control Circuit Design,Using UCC3818 as the PFC controller Voltage Loop Design Current Loop Design Critical Point of Bridgeless PFC,Voltage Loop Design 1,The pole is placed at the crossover frequency, is about 1020Hz, the zero is placed at the one tenth of the crossover frequency. The power stage gain is given by:,Voltage Loop Design 2,Voltage loopThe voltage amplifier configuration as right:Vref=7.5, so we choose: R125=R126=R127=332k, R129=19.6kVout=(332*3+19.6)*7.5/19.6=388VThe second harmanic voltage on the output capacitor is:The gain of the voltage amplifier is:,Voltage Loop Design 3,Voltage loop (continued)The value of Cf is determined by:The pole is place at the frequency:,Current Loop Design 1,Current loopThe gain of the power stage is:The current amplifier gain is:,Current Loop Design 2,Current loop (continued)The crossover frequency is 5KHz10KHz, the zero is placed at the crossover frequency to give a phase margin of 45 degrees. And a pole is placed at one-half the switching frequency to reduce switching noise.,Critical point of Bridgeless PFC,Due to the floating power GND, IAC cant be achieved by rectified line voltage directly in this circuit. We know IAC is |Vin|/R, so we just need have |Vin|. In this circuit, we can achieve |Vin| by filtering Vo*(1-D). D is the duty cycle of the driving signal of switches.,Critical point of Bridgeless PFC,The net introduces one pole at:The pole must be located at a frequency high enough not to distort the input waveform and at the same time, low enough to filter the switching frequency. We select fp = 10kHz, R1=600k, R2=7.5k, C=2200pF,Power Loss Calculation,Boost inductor,Power Loss Calculation,Main Switches,Power Loss Calculation,Power Loss Calculation,Boost Diode,