1 信号完整性分析及设计 2 课程安排 Parts 1: 信号完整性分析概述 Parts 2: 电源完整性分析 Parts 3: 高速电路设计分析技术 Parts 4: 高速PCB设计与仿真分析 3 信号完整性分析概述 1: 高速设计简介 2: 信号质量 3:传输线理论和传输线模型 - 反射 - 串扰 - 码间干扰(ISI) - SSN 4:器件模型 - 晶体管级模型 - IBIS模型 5: 管理信号质量 - 端接方案 - 拓扑结构 4 高速设计简介 What is Signal Integrity? 什么是信号完整性? A Circuit Example 一个电路实例 Purpose of SI 信号完整性研究的目的 5 6 什么是信号完整性(I) Dr. Howard Johnson: “Maximize the performance and minimize the cost of interconnection technology used in high-speed digital designs” 在高速数字设计中把互联结构的性能最大化,费用最小化 “Signal integrity is a field of study half-way between digital design and analog circuit theory. ” 信号完整性涉及到数字和模拟电路理论 From http:/www.sigcon.com 7 什么是信号完整性(II) An Engineering Practice 从工程学的角度来看, ? That ensures all signals transmitted are received correctly. 确保正确接收所传输的所有信号 ? That ensures signals do not interfere with one another in a way to degrade reception. 确保信号之 间不会相互干扰而损失接收信号的质量 ? That ensures signals do not damage any device. 确 保信号不会损害任何电器元件 ? That ensures signals do not pollute the electromagnetic spectrum. 确保信号不会污染电磁频 谱 8 90% 10% Rise Time DQS, DQS# DQ CLK ADDR DQS DQ CLK ADDR DQS DQ Matched length routing 235 Must adjust DQS timing for each lane to maintain CK/DQS relationship at SDRAM 必须调整DQS时序 (Write leveling) DQ shifts must follow DQS shifts DQ随着QDS移动 Controllers can adjust DQ/DQS output timing to simplify PCB routing 控制器可以调节DQ/DQS输出时序 CLK, CLK# ADDR Controller DQS, DQS# DQ DQS, DQS# DQ CLK ADDR DQS DQ CLK ADDR DQS DQ Matched length routing CK/CK# to DQS (and therefore DQ) 系统时钟和数据总线 (继续) 236 DQS/CLK Analysis CLKADDRL3 DQ DQS L2 DQ DQS L1 DQ DQS L0 DQ DQS CLK ADDR DQS DQ CLK ADDR DQS DQ CLK ADDR DQS DQ CLK ADDR DQS DQ 237 Adjusting DQ/DQS Timing 调节DQ/DQS输出时序 DQ/DQS aligned with CK/CK# on a per-byte lane basis 对每一路数据信号都要保持DQ/DQS与系统时钟的关系 Write Leveling DDR3 memory devices can report on alignment of received CK/DQS signals DDR3内存报告CK/DQS对齐信息给控制器 Controllers can utilize this information to optimize CLK/DQS/DQ output timing for each byte lane 控制器可以根据这个信息调整DQ/DQS输出时序 Read Leveling Controllers compensate for skew in signals returned from memory on a per-byte line basis 控制器可以补偿部分时序偏差 238 Adjusting Read Timing 调整读时序 Read out a predefined system timing calibration bit sequence 读入一个预先定义的数据序列 239 Write Leveling Concept 写时序 调节原理 思考：DDR2与DDR3内存地址走线拓扑 240 高速电路设计分析技术 High Speed Trends 高速设计趋势 Synchronous Design 同步系统设计 Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - Interconnect consideration 互连考虑 - Technologies 设计技术 - 8b/10b Encoding 8b/10b编码 241 SerialLink Design 高速串行设计 242 Serial I/O 高速串行接口 Jitter controlled is required due to CDR 抖动控制 Point to point topology 点对点拓扑 Pre/De-emphasis for driver end and equalization at receiver end due to loss in long interconnect 预加重和均衡电路设计 改善损耗影响 High-Performance serial signaling implemented with differential signaling technology 差分走线 parallel to serial conversion SERDES PLL serial to parallel conversion SERDES PLL serial link parallel data bus recovered parallel data bit clock 88 Figure 7.11 Generalized SERDES serial connection 243 Differential Impedance 差分 阻抗 ms ms oe CC LL Z + = ms ms oo CC LL Z + = oodiff ZZ2= oecomm ZZ 2 1 = Odd Mode Even Mode 思考：差分阻抗是两个单线阻抗之和么？ 244 Loosely & Tightly Coupled Diff Pair 松耦合和紧耦合 Loosely Coupled DP 松耦合 Differential Impedance depends only on single TL. Easy to do the layout, distance changes dont affect the differential impedance. 易于控制阻抗和布线 Tightly Coupled DP 紧耦合 High layout density, lower the cost. 布线密度大 Differential noise is smaller than Loosely Coupled DP. 差分噪声小 Common noise can be easily controlled by using common mode choke. 可以用共模扼流圈抑制共模噪声 Can minimize the influences of discontinuity in the ground plane current return pass. 可以减小不完整参考平面影响 思考：在高速Serial设计中， 要考虑的重点和采取松耦合还是紧耦合好 245 PCB structures that introduce Skew 差分走线偏差 An escape from a BGA or connector pins introduces skew BGA出线造成偏差 This is an example of skew compensation 一个控制偏差的例 子 思考： 差分走线正负延 时（Skew）会造成什么 246 Via Effect 过孔 Microstripline viaStripline via 247 Via Effect signal via couple with power/ground via 换层孔旁加地孔 Layer 2 and layer3 have same voltage attribute Power / ground vias closed to signal via which will play a role for return current path 信号孔旁的地孔可以提供回流路径 248 Right Angle Corner 直角走线 Capacitive effect 电容效果电容效果电容效果电容效果 Un continuous impedance 阻抗不连续阻抗不连续阻抗不连续阻抗不连续 Attenuate high frequency signals 高频信号衰减高频信号衰减高频信号衰减高频信号衰减 Ccorner Zo Zo 45obends, round and chamfered bends exhibit reduced effects 45o或圆角减小反射 249 Bends introduce skew 拐角造成偏差 Back to back bends compensate for skew 返回拐角控制偏差 Back to back bends compensate for 250 线宽影响线宽影响线宽影响线宽影响 思考： 损耗的成因和减小损耗的办法 251 Connector 连接器 Connector to be or not to be? 是否需要是否需要是否需要是否需要 Can you afford 2 connectors (in BP topology)? 添加俩个 连接器互连质量是否能够满足要求 Should you find a better connector? 是否有更好的连接器 252 Measurements of Gbps Signals - Connector Via Discontinuity 连接器造成的阻抗不连续 案例： 连接器串扰的分析 253 Time and Frequency Domain of Square