7. Microarchitecture of Superscalars (5) Dynamic Instruction Issue,Dezs Sima Fall 2006, D. Sima, 2006,Overview,1 The principle of dynamic instruction issue,2 Design space,2.1 Overview,2.2 Types of issue buffers,2.3 Operand fetch policies,4 Implementation of dynamic instruction issue in superscalars,4.1 The introduction of dynamic instruction issue,4.2 Basic implementation schemes,3 Principle of operation of dynamic instruction issue,3.1 Dispatch bound operand fetching,3.2 Issue bound operand fetching,5 Case examples,1. Principle of dynamic instruction issue (1),Aim:,To eliminate the issue bottleneck of early (first generation) supercalars,1. Principle of dynamic instruction issue (2),The issue bottleneck,(b): The issue process,(a): Simplified structure of the mikroarchitecture assuming unbuffered issue,Figure 1.1: The principle of dynamic instruction issue,Icache,I-buffer,Instr. window (3),Decode,check,issue,Dependent instructions,block instruction issue,1. Principle of dynamic instruction issue (3),Figure 1.2: Principle of dynamic instruction issue,(b): The issue process,(a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving),(shelving, buffered issue),Layout of the issue buffers,Scope of dynamic instr. issue,Instruction issue scheme,Dynamic instruction issue,Operand fetch policy,2. Design space of dynamic instruction issue,2.1 Overview,Types of issue buffers,2.2 Types of issue buffers,Reservation stations (RS),Issue buffers in the ROB,Types of issue buffers,Individual RSs,Central RS,Group RSs,Power1 (1990) PowerPC 603 (1993) PowerPC 604 (1995) Power4 (2001) Power5 (2004) K5 (1995) K7 (1999), K8 (2003),ES/9000 (1992) Power2 (1993) R10000 (1996) PM1(Sparc64)(1995) Alpha 21264 (1997),Pentium Pro (1995) Pentium II (1997) Pentium III (1999) Pentium IV (2000) Pentium M (2003) Core (2006),Lightning (1991)p K6 (1997),Layout of the issue buffers,Scope of buffered issue,Instruction issue scheme,Dynamic instruction issue,Operand fetch policy,Types of issue buffers,2.3 Operand fetch policies,Dispatch bound operand fetch policy,Issue bound operand fetch policy,Operand fetch policies,Decode / Issue,EU,Reg. file,OC,Rd,Op1/Rs1,Op2/Rs2,OC,I-buffer,Source reg. identifiers,Opcodes, destination reg. identifiers,Source 1 operands,Source 2 operands,EU,Rd, result,I-buffer,Source reg. identifiers,Opcodes, destination reg. identifiers,Source 1 operands,Source 2 operands,OC,Rd,IB,OC,Rd,Decode / Issue,Reg. file,EU,EU,Source reg. identifiers,IB,Rs1,Rs2,Dispatch,Issue,Dispatch,Issue,Figure 2.1: Operand fetch policies,3 Principle of operation of dynamic instruction issue,3.1 Dispatch bound operand fetching (1),Checking the availability of operands,Decode / Issue,EU,Reg. file,OC,Rd,Op1/Rs1,Op2/Rs2,OC,I-buffer,Source reg. identifiers,Opcodes, destination reg. identifiers,Source 1 operands,Source 2 operands,EU,Rd, result,Dispatch,Issue,V,V,V,V,V,3.1 Dispatch bound operand fetching (2),Updating the issue buffers,Decode / Issue,EU,Reg. file,OC,Rd,Op1/Rs1,Op2/Rs2,OC,I-buffer,Source reg. identifiers,Opcodes, destination reg. identifiers,Source 1 operands,Source 2 operands,EU,Rd, result,Dispatch,Issue,V,V,V,V,V,3.2 Issue bound operand fetching,Checking the availability of operands,I-buffer,Source reg. identifiers,Opcodes, destination reg. identifiers,Source 1 operands,Source 2 operands,OC,Rd,IB,OC,Rd,Decode / Issue,Reg. file,EU,EU,Source reg. identifiers,IB,Rs1,Rs2,Dispatch,Issue,V,4. Implementation of dynamic instruction issue in superscalars,4.1 The introduction of dynamic instruction issue,Figure 4.1: The introduction of dynamic instruction issue,Reservation stations (RS),Issue buffers in the ROB,Basic issue buffer schemes,Individual RSs,Central RS,Group RSs,Types of issue buffers,Operand fetch policy,Dispatch bound,Issue bound,Dispatch bound,Issue bound,Dispatch bound,Issue bound,Dispatch bound,Issue bound,PowerPC 603 (1993) PowerPC 604 (1995) K5 (1995),Power1 (1990) Power4 (2001) Power5 (2004) Nx586 (1994) K7 (1999), K8 (2003),PM1(Sparc64) (1995),ES/9000 (1992) Power2 (1993) R10000 (1996) Alpha 21264 (1997),Pentium Pro (1995) Pentium II (1997) Pentium III (1999),Pentium IV (2000) Pentium M (2003) Core (2006),Lightning (1991)p K6 (1997),4.2 Basic implementation schemes,5. Case example (1),Individual issue buffers,Figure 5.1: The microarchitecture of the Athlon,5. Case example (1),Individual issue buffers (2),Figure 5.2: Integer issue buffers of the K8L,Source: Malich, Y.AMDs Next Generation Microarchitecture Preview: from K8 to K8L”, Aug. 2006.,Issue buffers,Decoders,EUs,5. Case example (2),Group issue buffers,Figure 5.3: The microarchitecture o