10.3.1 K60 Signal Multiplexing and Pin AssignmentsThe following table shows the signals available on each pin and the locations of thesepins on the devices supported by this document. The Port Control Module is responsiblefor selecting which ALT functionality is available on each pin.144LQFP144MAPBGAPin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L5 RESERVEDRESERVEDRESERVED M5 NC NC NC A10 NC NC NC B10 NC NC NC C10 NC NC NC1 D3 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1 I2C1_SDA2 D2 PTE1/LLWU_P0ADC1_SE5aADC1_SE5aPTE1/LLWU_P0SPI1_SOUTUART1_RXSDHC0_D0 I2C1_SCL3 D1 PTE2/LLWU_P1ADC1_SE6aADC1_SE6aPTE2/LLWU_P1SPI1_SCKUART1_CTS_bSDHC0_DCLK4 E4 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_RTS_bSDHC0_CMD5 E5 VDD VDD VDD6 F6 VSS VSS VSS7 E3 PTE4/LLWU_P2DISABLED PTE4/LLWU_P2SPI1_PCS0UART3_TXSDHC0_D38 E2 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D29 E1 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS_bI2S0_MCLK I2S0_CLKIN10 F4 PTE7 DISABLED PTE7 UART3_RTS_bI2S0_RXD11 F3 PTE8 DISABLED PTE8 UART5_TXI2S0_RX_FS12 F2 PTE9 DISABLED PTE9 UART5_RXI2S0_RX_BCLK13 F1 PTE10 DISABLED PTE10 UART5_CTS_bI2S0_TXD14 G4 PTE11 DISABLED PTE11 UART5_RTS_bI2S0_TX_FS15 G3 PTE12 DISABLED PTE12 I2S0_TX_BCLK16 E6 VDD VDD VDD17 F7 VSS VSS VSS18 H3 VSS VSS VSS19 H1 USB0_DP USB0_DP USB0_DP20 H2 USB0_DMUSB0_DMUSB0_DMChapter 10 Signal Multiplexing and Signal DescriptionsK60 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 233144LQFP144MAPBGAPin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort21 G1 VOUT33 VOUT33 VOUT3322 G2 VREGIN VREGIN VREGIN23 J1 ADC0_DP1ADC0_DP1ADC0_DP124 J2 ADC0_DM1ADC0_DM1ADC0_DM125 K1 ADC1_DP1ADC1_DP1ADC1_DP126 K2 ADC1_DM1ADC1_DM1ADC1_DM127 L1 PGA0_DP/ADC0_DP0/ADC1_DP3PGA0_DP/ADC0_DP0/ADC1_DP3PGA0_DP/ADC0_DP0/ADC1_DP328 L2 PGA0_DM/ADC0_DM0/ADC1_DM3PGA0_DM/ADC0_DM0/ADC1_DM3PGA0_DM/ADC0_DM0/ADC1_DM329 M1 PGA1_DP/ADC1_DP0/ADC0_DP3PGA1_DP/ADC1_DP0/ADC0_DP3PGA1_DP/ADC1_DP0/ADC0_DP330 M2 PGA1_DM/ADC1_DM0/ADC0_DM3PGA1_DM/ADC1_DM0/ADC0_DM3PGA1_DM/ADC1_DM0/ADC0_DM331 H5 VDDA VDDA VDDA32 G5 VREFH VREFH VREFH33 G6 VREFL VREFL VREFL34 H6 VSSA VSSA VSSA35 K3 ADC1_SE16/CMP2_IN2/ADC0_SE22ADC1_SE16/CMP2_IN2/ADC0_SE22ADC1_SE16/CMP2_IN2/ADC0_SE2236 J3 ADC0_SE16/CMP1_IN2/ADC0_SE21ADC0_SE16/CMP1_IN2/ADC0_SE21ADC0_SE16/CMP1_IN2/ADC0_SE2137 M3 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE1838 L3 DAC0_OUT/CMP1_IN3/ADC0_SE23DAC0_OUT/CMP1_IN3/ADC0_SE23DAC0_OUT/CMP1_IN3/ADC0_SE2339 L4 DAC1_OUT/CMP2_IN3/ADC1_SE23DAC1_OUT/CMP2_IN3/ADC1_SE23DAC1_OUT/CMP2_IN3/ADC1_SE2340 M7 XTAL32 XTAL32 XTAL3241 M6 EXTAL32 EXTAL32 EXTAL3242 L6 VBAT VBAT VBATPinoutK60 Sub-Family Reference Manual, Rev. 6, Nov 2011234 Freescale Semiconductor, Inc.144LQFP144MAPBGAPin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort43 VDD VDD VDD44 VSS VSS VSS45 M4 PTE24 ADC0_SE17ADC0_SE17PTE24 CAN1_TX UART4_TX EWM_OUT_b46 K5 PTE25 ADC0_SE18ADC0_SE18PTE25 CAN1_RXUART4_RX EWM_IN47 K4 PTE26 DISABLED PTE26 UART4_CTS_bENET_1588_CLKINRTC_CLKOUTUSB_CLKIN48 J4 PTE27 DISABLED PTE27 UART4_RTS_b49 H4 PTE28 DISABLED PTE2850 J5 PTA0 JTAG_TCLK/SWD_CLK/EZP_CLKTSI0_CH1PTA0 UART0_CTS_bFTM0_CH5 JTAG_TCLK/SWD_CLKEZP_CLK51 J6 PTA1 JTAG_TDI/EZP_DITSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI52 K6 PTA2 JTAG_TDO/TRACE_SWO/EZP_DOTSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/TRACE_SWOEZP_DO53 K7 PTA3 JTAG_TMS/SWD_DIOTSI0_CH4PTA3 UART0_RTS_bFTM0_CH0 JTAG_TMS/SWD_DIO54 L7 PTA4/LLWU_P3NMI_b/EZP_CS_bTSI0_CH5PTA4/LLWU_P3FTM0_CH1 NMI_b EZP_CS_b55 M8 PTA5 DISABLED PTA5 FTM0_CH2RMII0_RXER/MII0_RXERCMP2_OUTI2S0_RX_BCLKJTAG_TRST56 E7 VDD VDD VDD57 G7 VSS VSS VSS58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_CLKOUT59 J8 PTA7 ADC0_SE10ADC0_SE10PTA7 FTM0_CH4 TRACE_D360 K8 PTA8 ADC0_SE11ADC0_SE11PTA8 FTM1_CH0 FTM1_QD_PHATRACE_D261 L8 PTA9 DISABLED PTA9 FTM1_CH1MII0_RXD3 FTM1_QD_PHBTRACE_D162 M9 PTA10 DISABLED PTA10 FTM2_CH0MII0_RXD2 FTM2_QD_PHATRACE_D063 L9 PTA11 DISABLED PTA11 FTM2_CH1MII0_RXCLKFTM2_QD_PHB64 K9 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD1/MII0_RXD1I2S0_TXDFTM1_QD_PHA65 J9 PTA13/LLWU_P4CMP2_IN1CMP2_IN1PTA13/LLWU_P4CAN0_RXFTM1_CH1RMII0_RXD0/MII0_RXD0I2S0_TX_FSFTM1_QD_PHBChapter 10 Signal Multiplexing and Signal DescriptionsK60 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 235144LQFP144MAPBGAPin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort66 L10 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TXRMII0_CRS_DV/MII0_RXDVI2S0_TX_BCLK67 L11 PTA15 DISABLED PTA15 SPI0_SCKUART0_RXRMII0_TXEN/MII0_TXENI2S0_RXD68 K10 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS_bRMII0_TXD0/MII0_TXD0I2S0_RX_FS69 K11 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS_bRMII0_TXD1/MII0_TXD1I2S0_MCLKI2S0_CLKIN70 E8 VDD VDD VDD71 G8 VSS VSS VSS72 M12 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2FTM_CLKIN073 M11 PTA19 XTAL XTAL PTA19 FTM1_FLT0FTM_CLKIN1LPT0_ALT174 L12 RESET_b RESET_b RESET_b75 K12 PTA24 DISABLED PTA24 MII0_TXD2 FB_A2976 J12 PTA25 DISABLED PTA25 MII0_TXCLKFB_A2877 J11 PTA26 DISABLED P