DRAM工作原理 DRAM工作原理,Dynamic Random Access Memory Each cell is a capacitor + a transistor Very small size SRAM uses six transistors per cell Divided into banks, rows & columns Each bank can be independently controlled,DRAM,Main Memory Everything that happens in the computer is resident in main memory Capacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanoseconds Why DRAM for Main Memory ? Cost effective (small chip area than SRAM) High Speed(than HDD, flash) High Density(Gbyte) Mass Production ,Main memory,Notation: K, M, G In standard scientific nomenclature, the metric modifiers K, M, and G to refer to factors of 1,000, 1,000,000 and 1,000,000,000 respectively. Computer engineers have adopted K as the symbol for a factor of 1,024 (210 ) K: 1,024 (210 ) M: 1,048,576 (220 ) G: 1,073,741,824 (230 ) DRAM density 256M-bit 512M-bit,DRAM Density,What is a DRAM? DRAM stands for Dynamic Random Access Memory. Random access refers to the ability to access any of the information within the DRAM in random order. Dynamic refers to temporary or transient data storage. Data stored in dynamic memories naturally decays over time. Therefore, DRAM need periodic refresh operation to prevent data loss.,Memory: DRAM position Semiconductor memory device ROM: Non volatile Mask ROM EPROM EEPROM Flash NAND: low speed, high density NOR: high speed, low density RAM: Volatile DRAM: Dynamic Random Access Memory SRAM: Static Random Access Memory Pseudo SRAM,DRAM Trend : Future High Speed - DDR(333MHz500MHz), DDR2(533800Mbps), DDR3(8001600Mbps) - Skew-delay minimized circuit/logic : post-charge logic, wave-pipelining - New Architecture : multi-bank structure, high speed Interface Low Power - 5.5V = 3.3V(sdr) = 2.5V(ddr) = 1.8V(ddr2) = 1.5v (ddr3) = 1.2v? - Small voltage swing I/O interface : LVTTL to SSTL, open drain - Low Power DRAM(PASR, TCSR, DPD) High Density - Memory density: 32MB = 64MB = . 1GB = 2GB = 4GB - application expansion : mobile, memory DB for shock (than HDD) - Process shrink :145nm(03) =120nm(04) = 100nm = 90nm = 80nm Other Trends - Cost Effectiveness, Technical Compatibility, Stability, Environment. Reliability,Static RAM,SRAM Basic storage element is a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive power No need for a periodic refreshing signal or a clock Used in system cache Fastest memory, but expensive,Dynamic RAM,DRAM Denser type of memory Made up of one-transistor (1-T) memory cell which consists of a single access transistor and a capacitor Cheaper than SRAM Used in main memory More complicated addressing scheme,Refresh in DRAMs,Capacitor leaks over time, the DRAM must be “REFRESHED”.,Capacitance Leakage,SRAM vs. DRAM,DRAM Lead Frame and Wire bonding,DRAM Architecture,SDRAM has the multi bank architecture. Conventional DRAM was product that have single bank architecture. The bank is independent active. memory array have independent internal data bus that have same width as external data bus. Every bank can be activating with interleaving manner. Another bank can be activated while 1st bank being accessed. (Burst read or write),Multi Bank Architecture,DRAM Multi Bank Architecture,DRAM Single Bank Architecture,DRAM Block Diagram(1),DRAM Block Diagram(2),DRAM Core Architecture,DRAM Address,DRAM Core Architecture,16bit DRAM Core,DRAM Data Path,DRAM 1T-1C structure,RAS: row address strobe CAS: column address strobe WE: write enable Address: code to select memory cell location DQ (I/O): bidirectional channel to transfer and receive data DRAM cell: storage element to store binary data bit Refresh: the action to keep data from leakage Active: sense data from DRAM cell Pre charge: standby state,DRAM Key word,DRAM cell array consist of so many cells. One transistor & One capacitor Small sense amplifier Low input gain from charge sharing CS : Small storage capacitor: 25fF CBL : Large parasitic capacitor: over 100fF Vc: Storage voltage VCP : half Vc for plate bias VBLP : half Vc for BL pre charge bias (initial bias),DRAM Cell,DRAM Array Overview,Simplified Example,Activating a Row,Activating a Row Must be done before a read or write Just latch the row address and turn on a single wordline,Writing,Writing A row must be active Select the column address Drive the data through the column mux Stores the charge on a single capacitor,Reading,Reading A row must be active Select the column address The value in the sense-amplifier is driven back out,The Sense-Amplifier,Sense-Amplifier A pair of cross-coupled inverters Basically an SRAM element Weaker than the column mux Write data will “outmuscle” the sense-amplifier Keeps the data at full level,Precharge,Precharge Inactive state (no wordlines active) Precharge control line high Ties the two sides of the sense-amp together This makes the bitlines stay at VDD/2 Only stable as long as the precharge con