Sitronix ST7571 4 Gray Scale Dot Matrix LCD Controller/Driver Ver 1.5a 1/76 2009/7/21 1. INTRODUCTION ST7571 is a driver Delay (100); / Delay 100ms for stable VDD1/VDD2/VDD3 Write(COMMAND, 0xAE); / Display OFF Write(COMMAND, 0x38); / MODE SET Write(COMMAND, 0xB8); / FR=1011 = 85Hz / BE1:0=1,0 = booster efficiency Level-3 Write(COMMAND, 0xA1); / ADC select, ADC=1 =reverse direction Write(COMMAND, 0xC8); / SHL select, SHL=1 = reverse direction Write(COMMAND, 0x44); / Set initial COM0 register Write(COMMAND, 0x00); / Write(COMMAND, 0x40); / Set initial display line register Write(COMMAND, 0x00); / Write(COMMAND, 0xAB); / OSC. ON Write(COMMAND, 0x67); / DC-DC step up, 8 times boosting circuit Write(COMMAND, 0x25); / Select regulator register(1+(Ra+Rb) Write(COMMAND, 0x81); / Set Reference Voltage Write(COMMAND, 0x23); / EV=35 = Vop =10.556V Write(COMMAND, 0x54); / Set LCD Bias=1/9 V0 Write(COMMAND, 0xF3); / Release Bias Power Save Mode Write(COMMAND, 0x04); / Write(COMMAND, 0x93); / Set FRC and PWM mode (4FRC / Power Control, VC: ON VR: OFF VF: OFF Delay (200); / Delay 200ms Write(COMMAND, 0x2E); / Power Control, VC: ON VR: ON VF: OFF Delay (200); / Delay 200ms Write(COMMAND, 0x2F); / Power Control, VC: ON VR: ON VF: ON Delay (10); / Delay 10ms Write(COMMAND, 0xAF); / Display ON Note: The initial code is for reference only. An optimized initial code should be checked on customers system and LCD module. ST7571 Ver 1.5a 51/76 2009/7/21 10.3 Referential Operation Flow : Displaying Data Fig. 27 Data Displaying Flow 10.4 Referential Operation Flow : Set Color Mode (Black/White Mode) Enter Test Command Set 3 Write( COMMAND, 0x7B ); Exit Test Command Set 3 Write( COMMAND, 0x00 ); Black/White Mode Gray Mode (default) Set Color Mode Write( COMMAND, 0x11 ); ST7571 Ver 1.5a 52/76 2009/7/21 10.5 Referential Operation Flow : Power-OFF By setting 0xA9, ST7571 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are turned OFF and a discharge process starts. Instruction Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed. Fig. 28 Power off instruction flow Note: 1. tPOFF: Internal Power discharge time. = 250ms (max). 2. tV2OFF: Period between VDD1 and VDD2 OFF time. = 0 ms (min). 3. It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. 5. The timing is dependent on panel loading and the external capacitor(s). 6. The timing in these figures is base on the condition that: LCD Panel Size = 1.8” and C=1uF. 7. When turning VDD2 OFF, the falling time should follow the specification: 300ms tPFall 1sec ST7571 Ver 1.5a 53/76 2009/7/21 10.6 Referential Operation Flow : Burning EEPROM HW Reset Remove VDD from VE Remove 18V from VPP VPP connect to 18V VE connect to VDD Delay 120ms Disable Autoread Initial Sequence Show Image Erase EE Write EE ( Software Coding Flow) Set EE Register (for the best display quality) HW Reset Delay 120ms Check Module Performance Read EE + - 0x51 Key Adjust Vop Offset 0x52 ( Software Coding Flow) Fig. 19 EE Burning flow chart ST7571 Ver 1.5a 54/76 2009/7/21 Referential Software Functions void Disable_autoread(void) Write(COMMAND, 0xD1); /Enter test command set 2 Write(COMMAND, 0xAA); /Disable auto-read Write(COMMAND, 0x00); /Enter normal mode void Read_EE (void) Write(COMMAND, 0xD1); /Enter test command set 2 Write(COMMAND, 0xAA); /Auto-read disable Write(COMMAND, 0x13); /Enter EEPROM mode Write(COMMAND, 0x20); /Enable read mode Delay(200); /Delay 200ms Write(COMMAND, 0x71); /Set read pulse Delay(200); /Delay 200ms Write(COMMAND, 0x83); /Exit EEPROM mode Write(COMMAND, 0x00); /Enter normal mode void Set_EE _Register (void) / Adjust Vop offset here / Command 0x51 and 0x52 can be set 16 times for adjusting a suitable Vop / Maxmum adjusting ranges are +/-16 levels. Write(COMMAND, 0xFD); /Enter test command set 1 Write(COMMAND, 0x8C); Write(COMMAND, 0x90); /Set Vop offset highest bit Vop_j4=0 /Set Vop offset Vop_j3:0=0 Write(COMMAND, 0x51); or Write(COMMAND, 0x52); /0x51 for increase Vop offset by 1 level /0x52 for decrease Vop offset by 1 level Write(COMMAND, 0x00); /Enter normal mode ST7571 Ver 1.5a 55/76 2009/7/21 void Erase_EE (void) Write(COMMAND, 0xD1); /Enter test command set 2 Write(COMMAND, 0x13); /Enter EEPROM mode Write(COMMAND, 0x4A); /Enable erase mode Delay(200); /Delay 200ms Write(COMMAND, 0x55); /Set erase pulse Delay(200); /Delay 200ms Write(COMMAND, 0x83); /Exit EEPROM mode Write(COMMAND, 0x00); /Enter normal mode void Write_EE (void) Write(COMMAND, 0xD1); /Enter test command set 2 Write(COMMAND, 0x13)