GigaDevice Semiconductor Inc.GD32F105xxARM Cortex-M3 32-bit MCUDatasheet北京锐鑫同创科技有限公司 GD32F105xxTable of ContentsList of Figures3List of Tables41 General description52 Device overview62.1 Device information62.2 Block diagram82.3 Pinouts and pin assignment92.4 Memory map122.5 Clock tree132.6 Pin definitions143 Functional description223.1 ARM Cortex-M3 core223.2 On-chip memory223.3 Clock, reset and supply management233.4 Boot modes233.5 Power saving modes243.6 Analog to digital converter (ADC)243.7 Digital to analog converter (DAC)253.8 DMA253.9 General-purpose inputs/outputs (GPIOs)253.10 Timers and PWM generation263.11 Real time clock (RTC)273.12 Inter-integrated circuit (I2C)273.13 Serial peripheral interface (SPI)283.14 Universal synchronous asynchronous receiver transmitter (USART)283.15 Inter-IC sound (I2S)283.16 Universal serial bus on-the-go full-speed (USB OTG FS)293.17 Controller area network (CAN)293.18 External memory controller (EXMC)293.19 Debug mode303.20 Package and operation temperature304 Electrical characteristics314.1 Absolute maximum ratings314.2 Recommended DC characteristics314.3 Power consumption324.4 EMC characteristics334.5 Power supply supervisor characteristics334.6 Electrical sensitivity344.7 External clock characteristics341 / 434.8 Internal clock characteristics354.9 PLL characteristics364.10 Memory characteristics364.11 GPIO characteristics364.12 ADC characteristics374.13 DAC characteristics374.14 I2C characteristics374.15 SPI characteristics385 Package information396 Ordering Information417 Revision History422 / 43List of FiguresFigure 1. GD32F105xx block diagram8Figure 2. GD32F105Zx LQFP144 pinouts9Figure 3. GD32F105Vx LQFP100 pinouts10Figure 4. GD32F105Rx LQFP64 pinouts11Figure 6. GD32F105xx memory map12Figure 7. GD32F105xx clock tree13Figure 8. LQFP package outline393 / 43List of TablesTable 1. GD32F105xx devices features and peripheral list6Table 2. GD32F105xx pin definitions14Table 3. Absolute maximum ratings31Table 4. DC operating conditions31Table 5. Power consumption characteristics32Table 6. EMS characteristics33Table 7. EMI characteristics33Table 8. Power supply supervisor characteristics33Table 9. ESD characteristics34Table 10. Static latch-up characteristics34Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics34Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics35Table 13. High speed internal clock (HSI) characteristics35Table 14. Low speed internal clock (LSI) characteristics35Table 15. PLL characteristics36Table 16. Flash memory characteristics36Table 17. I/O port characteristics36Table 18. ADC characteristics37Table 19. DAC characteristics37Table 20. I2C characteristics37Table 21. SPI characteristics38Table 22. LQFP package dimensions40Table 23. Part ordering code for GD32F105xx devices41Table 24. Revision history424 / 431 General descriptionThe GD32F105xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM Cortex-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.The GD32F105xx device incorporates the ARM Cortex-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USB OTG FS.The device operates from a 2.6 to 3.6 V power supply and available in 40 to +85 C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.The above features make the GD32F105xx devices suitable for a wide range of applications, especial