计算机组成原理实验报告评语:课中检查完成的题号及题数： 课后完成的题号与题数：成绩:指导教师:实验报告实验名称：基于硬布线控制器设计并实现带中断功能的复杂模型机日期：2011-1-12班级：学号：姓名：一、实验目的：1.掌握硬布线控制器的组成原理、设计方法；2.了解硬布线控制器和微程序控制器的各自优缺点；3.掌握并会设计带中断功能的复杂模型机的硬布线控制器。二、实验内容：1.根据带中断功能的复杂模型机的微程序流图，画出状态机描述图；2.分析每个状态所需的控制信号，产生控制信号表，并用VHDL语言来设计程序，实现状态机描述的功能；3.用Quartus软件进行编译链接，选择器件，定义管脚，编程下载，然后用CM3P联机测试每一条机器指令的功能。 三、项目要求及分析： 实验要求设计带中断功能的复杂模型机的硬布线控制器，可先参照前面带中断处理能力的模型机设计实验画出微程序流程图，参照二进制微代码表设控制信号表。然后用VHDL语言编程实现，主要注意原PP的修改，采用分支语句实现。然后就是连线装载带中断处理能力的模型机微程序检验。 四、具体实现： 应包括：状态图、控制信号表、控制引脚图、VHDL程序、机器码验证程序等。1、状态图： 2、控制状态表：INTA/WR/RD/IOM/S3/S2/S1/S0/LDA/LDB/LDR0/LDSP/L0AD/LDAR/LDIR/ALUB/RSB/RDB/RIB/SPB/PCB/LDPC/STI/CLIS0 100000000000100111111010S1 100000000000100111111011S2 100000000000110111110111S3 101000000000101111111011S4 100000000100100101111011S5100010010010100011111011S6100000000100100101111011S7 100000100010100011111011S8101000000000110111111011S9101100000010100111111011S10101000000000110111111011S11100000000000100111111011S12101000000010100111111011S13110000000000100110111011S14100000000000000011111111S15100000000000100111111011S16110100000000100101111011S17101000000010100111111011S18110000000000100101111011S19100000001000100111101011S20100011010001100011111011S21100011000001100011111011S22100000000000110111101011S23101000000010100111111011S24100011000001100011111011S25100000000000110111101011S26101000000000000111111111S27100000000000000011111111S28101000001000100111111011S29101000000000110111111011S30101000000000110111111011S31101000001000100111111011S32101000000000110111111011S33000000000000110111101011S34110000000000100111110011S35100000001000100111101011S36100011010001100011111011S37000000000000110111111011S38101000000000000111111111S39101000001000100111111011S40100000000100100111011011S41100010010000110011111011S42100010011000100011111011S43101000001000100111111011S44100000000100100111110011S45100010010000110011111011S46100010011000100011111011S47100000001000100110111011S48100000001000100110111011S49100000000000110111110111S50100000000000110111110111S51100000000010100101111011S52100000000000100111111011S53100000000000110111110111S54100000000000100111111001S55100000000000100111111010S56100000000000110111101011S57100000001000100111101011S58100000001000100111101011S59100000000000110111110111S60100000000000110111110111S61100000000000110111110111S621000000000001101111101113、控制引脚图：五、调试运行结果： 4、VHDL程序：LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY CONTROLLER ISPORT(RESET: INSTD_LOGIC;T1: INSTD_LOGIC;INTR : IN STD_LOGIC;INS : INSTD_LOGIC_VECTOR(7 DOWNTO 0);CTRL : OUTSTD_LOGIC_VECTOR(23 DOWNTO 0);END CONTROLLER;ARCHITECTURE CONTROLLER_ARCH OF CONTROLLER ISTYPE STATE IS (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39,S40,S41,S42,S43,S44,S45,S46,S47,S48,S49,S50,S51,S52,S53,S54,S55,S56,S57,S58,S59,S60,S61,S62);SIGNAL CUFSM: STATE;-CTRL:INTA,WR,RD,IOM,S3,S2,S1,S0,LDA,LDB,LDRI,LDSP,LOAD,LDAR,LDIR,ALU_B,RS_B,RD_B,RI_B,SP_B,PC_B,LDPC,STI,CLIBEGINPROCESS (T1,RESET,INTR,INS)BEGINIF RESET = 0 THEN CTRL = 100000000000100111111010; -CLICUFSM CTRL = 100000000000100111111011; -中断判断CUFSM IF INTR=1 THEN CTRL BUS,BUS-ACUFSM = S33;ELSE CTRL = 100000000000110111110111; CUFSM CTRL = 110000000000100111110011; CUFSM CTRL = 100000001000100111101011; CUFSM CTRL = 100011010001100011111011; CUFSM CTRL = 000000000000110111111011; CUFSM CTRL = 101000000000000111111111; CUFSM CTRL = 100000000000110111110111; CUFSM CTRL = 101000000000101111111011; CUFSM IF INS(7 downto 4) = 0000 THEN -ADD INSCTRL = 100000001000100110111011; CUFSM = S47;ELSIF INS(7 downto 4) = 0001 THEN -AND INSCTRL = 100000001000100110111011; CUFSM = S48;ELSIF INS(7 downto 4) = 0010 THEN - IN INSCTRL = 100000000000110111110111; CUFSM = S49;ELSIF INS(7 downto 4) = 0011 THEN -OUT INSCTRL = 100000000000110111110111; CUFSM = S50;ELSIF