资源预览内容
第1页 / 共5页
第2页 / 共5页
第3页 / 共5页
第4页 / 共5页
第5页 / 共5页
亲,该文档总共5页全部预览完了,如果喜欢就下载吧!
资源描述
VHDL调用Verilog模块的时候,要在实例化模块前,加上“verilogmodelGM:”VHDL 调用 verlogverilog module:module m(a,b,c);input a,b;output c;endmodule调用如下:compoent mport(a: in std_logic;b: in std_logic;c: out std_logic);end compoentbeginverilogmodelGE: mport map()end在VHDL里调用Verilog的话:例化+映射在Verilog里调用VHDL的话:只要映射 看的别人的。被骗了,所以发点实在的,VHDL与verilog调用这里用VHDL调用VERILOG写好的模块.先按VHDL的语法声明实体(也就是你用Verilog写的模块),然后按VHDL的语法例化实 体就行了 .这样就不用转换了,或者可以少用转换了.例子.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.dt16_pkg.all;entity clk_alm isport (reset:instd_logic;fck32m:instd_logic;- 自背板的 32M 帧头clk32m: instd_logic;-自背板的 32M 时钟refclk2m: instd_logic; 2M 参考时钟clklos:outstd_logic时钟告警输出);end clk_alm;architecture arch_clk_alm of clk_alm iscomponent clk_dogport(reset : in std_logic;clock : in std_logic;-work clockrefclk : in std_logic;-reference clockalm : out std_logic);end component;component ALM 一声明port(XMCLK: in std_logic;RST : in std_logic;M_CLK : in std_logic;LOST_ALM : out std_logic);end component;signal alm_clk: std_logic;signal alm_fck: std_logic;signal refclk2m_div: std_logic;signal count: std_logic_vector(2 downto 0);signal delay_los: std_logic;beginclk_dog0: clk_dogport map (reset = reset ,clock=clk32m ,refclk =refclk2m , alm =alm_clk);fck_dog0:PORT MAP(ALM -例化XMCLK=RST=M_CLK=LOST_ALM = );fck32m ,reset ,refclk2m_div ,alm_fckprocess(reset,refclk2m)beginif reset=1 thencount0);elsif refclk2mevent and refclk2m=1 thencount=count+1;end if;end process;refclk2m_div=count(2);clklos=not(alm_clk and alm_fck);end arch_clk_alm;以下是 verilog 写的 modulemodule ALM (XMCLK, RST, M_CLK, LOST_ALM);input XMCLK ;input RST ;input M_CLK ;output LOST_ALM ;reg LOST_ALM;reg 2:0ALM_STATE;reg 2:0COUNTA;reg 2:0COUNTB;reg 2:0COUNTC;always (negedge RST or posedge XMCLK) begin if (!RST) COUNTA = 0;else if (COUNTA = 7)COUNTA = 0;else COUNTA = COUNTA + 1;end always (posedge M_CLK)beginif (!RST)beginCOUNTB = 0;COUNTC = 0;endelsebeginCOUNTC = COUNTB;COUNTB = COUNTA;endendalways (negedge M_CLK)beginif (!RST)ALM_STATE = 0;else if (ALM_STATE = 7)ALM_STATE = 0;else if (COUNTC = COUNTB)ALM_STATE = ALM_STATE + 1;else ALM_STATE = 0;endalways (posedge M_CLK)beginif (!RST)LOST_ALM = 1;else if (ALM_STATE = 7)LOST_ALM = 0;else LOST_ALM = 1;endendmodule
网站客服QQ:2055934822
金锄头文库版权所有
经营许可证:蜀ICP备13022795号 | 川公网安备 51140202000112号