-分频器library ieee;use ieee.std_logic_1164.all;entity fenpin is port(clk:in std_logic; qH: buffer std_logic; qout:buffer std_logic);end entity;architecture c20 of fenpin is begin process(clk) variable num : integer :=1; variable num1 : integer :=1 begin if clkevent and clk=0 then if(num=2)-0000000) -1HZ- to timer then num:=1;qout=not qout; else num:=num+1; end if; if(num1=1)-000000) -1000HZ-10000 to wei then num1:=1;qH=not qH; else num1:=num1+1; end if; end if;end process;end c20;-timerlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Clock3 is port(clk:in std_logic; duan: out std_logic_vector(3 downto 0); wei: in std_logic_vector(2 downto 0); wei2: out std_logic_vector(2 downto 0) );end entity;architecture clo of Clock3 is signal clk2:std_logic ; signal keys: std_logic_vector(2 downto 0); begin keys=key_h&key_m&key_s; clk2=clk or flag; process(key_que) begin if key_queevent and key_que=0 then flag if clk2event and clk2=0 then -正常计时 if scn=59 and min=59 and hor=23 then scn:=0;min:=0;hor:=0; elsif scn=59 and min=59 then scn:=0;min:=0;hor:=hor+1; elsif scn=59 then scn:=0;min:=min+1; else scn:=scn+1; end if; if min=59 -整点报时500hz then if scn=50 or scn=52 or scn=54 or scn=56 or scn=58 then music_out=musicL; else music_out=0; end if; elsif min=0 and scn=0-整点报时1000HZ then music_out=musicH; else music_out case keys is when 011 = if hor=23 then hor:=0; else hor:=hor+1; end if; -keys if min=59 then min:=0; else min:=min+1; end if; - keys if scn=59 then scn:=0; else scn:=scn+1; end if; - keys null;- keys=00; end case; end case; h:=hor/10; -除法，尤其是取余数运算会占用诸多逻辑资源 hH=0000+h; hL=0000+(hor-10*h); m:=min/10; mH=0000+m; mL=0000+(min-10*m); s:=scn/10; sH=0000+s; sL key_out key_out null; end case; end if; end process; key_qudou;-顶层文献 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Clock is port( clk:in std_logic; music_out:out std_logic; key_in:in std_logic; keyh_in:in std_logic; keym_in:in std_logic; keys_in:in std_logic; duan: out std_logic_vector(6 downto 0); wei: buffer std_logic_vector(2 downto 0);end entity;architecture clo of Clock is component fenpin port(clk:in std_logic; musicH: buffer std_logic; musicL: buffer std_logic; qH: buffer std_logic; qM: buffer std_logic; qout:buffer std_logic); end component; component counter_8 port( clk: in std_logic; count: buffer std_logic_vector(2 downto 0); end component; component Clock3 port(clk:in std_logic; key_que:in std_logic; key_h:in s