MAX II CPLD: Lowest Power, Lowest Cost CPLD Family Ever Alteras MAX II family of CPLD family are the lowest power, lowest cost CPLDs ever. MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II CPLD MAX IIG CPLD MAX IIZ CPLD This instant-on, non-volatile CPLD family targets general-purpose, low-density logic andportable applications, such as cellular handset design. In addition to delivering the lowest cost for traditional CPLD designs, the MAX II CPLD drives power and cost improvements to higher densities, enabling you to use a MAX II CPLD in place of a higher power or higher cost ASSP or and standard-logic CPLD. Advanced CPLD features The MAX II CPLD enables a high level of functional integration to reduce system design costs. This section describes the advanced features found in every MAX II CPLD. Low power CPLD One-tenth the power consumption (compared toa previous-generation 3.3-VMAX CPLD) 1.8-V core voltage for reduced power consumption and increased reliability CPLD industrys lowest standby specification, allowing longer usein battery powered applications Auto start/stop capability for turning off the CPLD when not in use Cost-optimized architecture Four times the density at half the price (compared to previous MAXCPLD generations) Designedfor minimum die size, giving the lowest cost per I/O pin in the industry High performance Support for internal clock frequency rates of up to 300 MHz Twicethe performance (compared to a 3.3-V MAX CPLD) Unique features On-board oscillatorand userflashmemory Reduces chip count by eliminating discrete oscillators ornon-volatile storage devices Real-time in-system programmability (ISP) Capable of downloading a second design while the device is operational Reduces the cost of remote field updates MultiVolt core flexibility On-chip voltage regulator accepts 3.3-V, 2.5-V, or 1.8-V supply Simplifies board design with fewer power rails Parallel flash loader megafunction Improves configuration efficiency of non-JTAG-compliant flash devices on the board Simplifies board management by allowing JTAG command implementation via the MAX IICPLD I/O capabilities MultiVolt I/O capability allows interface with devices at 1.5-V, 1.8-V, 2.5-V, or 3.3-V logic levels Schmitt triggers, programmable slew rate, andprogrammable drive strength improve signal integrity Easiest-to-use software Alteras no-cost QuartusII Web Edition software supports all devices in the MAX II CPLD familyandoptimizes pin-locked fittingand performance New MAX+PLUSII look-and-feel option in the Quartus II software enhances ease of use CPLD Applications The MAX II CPLD family targets common control path applications, including: Power-up sequencing System configuration I/O expansion Interface bridging MAX II CPLD系列概述及应用 Altera的MAX II 系列CPLD是有史以来功耗最低、成本最低的CPLD。MAX II CPLD基于突破性的体系结构，在所有CPLD系列中，其单位I/O引脚的功耗和成本都是最低的。随着MAX IIZ的推出，有三种型号产品都使用了同样的创新CPLD体系结构： MAX II CPLD MAX IIG CPLD MAX IIZ CPLD 这一瞬时接通的非易失器件系列面向蜂窝手机设计等通用低密度逻辑应用。不但具有传统CPLD设计的低成本特性，MAX II CPLD还进一步提高了高密度产品的功耗和成本优势，这样，您可以使用MAX II CPLD来替代高功耗和高成本ASSP以及标准逻辑CPLD。 MAX II 器件系列的高级特性 MAX II CPLD支持高级功能集成，以降低系统设计成本。这一部分介绍MAX II CPLD的高级特性。 低功耗 十分之一的功耗 (和前一代3.3V MAX器件相比) 1.8V内核电压降低了功耗，提高可靠性。 CPLD业界最低的待机规范，大大延长了电池供电时间。 自动启动/停止功能，CPLD不使用时关断。 低成本体系结构 以一半的价格实现四倍的密度 (和前一代 MAX 器件相比) 通过设计，减小了管芯面积，单位I/O引脚成本在业界是最低的。 高性能 支持高达300 MHz的内部时钟频率 性能加倍(和3.3-V MAX器件相比 ) 独特的特性 板上振荡器和用户闪存 不需要分立振荡器或者非易失存储器，减少了芯片数量。 实时在系统可编程能力(ISP) 器件工作时，可下载第二个设计。 降低了远程现场更新的成本 灵活的MultiVolt内核 片内电压稳压器支持3.3-V、2.5-V和1.8-V供电 减少了电源数量，简化了电路板设计。 并行闪存加载程序宏功能 提高了板上不兼容JTAG闪存的配置效率 通过MAX II 器件实现JTAG命令，简化了电路板管理。 I/O能力 MultiVolt I/O支持和1.5-V、1.8-V、2.5-V以及3.3-V逻辑电平器件的接口 施密特触发器、可编程摆率和可编程驱动能力提高了信号完整性 使用方便的软件 Altera免费的Quartus II 网络版软件支持所有的MAX II CPLD，优化了引脚锁定适配，提高了性能。 Quartus II 软件中新的MAX+PLUS II “look-and-feel”选项增强了软件的易用性 MAX II CPLD应用 MAX II 器件面向常见的控制通道应用，包括： 上电排序 系统配置 I/O扩展 接口桥接