3D7220G-.75中文资料MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7220) FEATURES ? All-silicon, low-power CMOS technology? TTL/CMOS compatible inputs and outputs? Vapor phase, IR and wave solderable? Auto-insertable (DIP pkg.)? Low ground bounce noise? Leading- and trailing-edge accuracy ? Delay range: 0.75ns through 7000ns ? Delay tolerance: 2% or 0.5ns ? Temperature stability: 2% typical (-40C to 85C)? Vdd stability: 1% typical (4.75V-5.25V)? Minimum input pulse width: 15% of total delay? 14-pin Gull-Wing available as drop-inreplacement for hybrid delay lines FUNCTIONAL DESCRIPTION The 3D7220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.The all-CMOS 3D7220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.PACKAGES 1413121110981234567IN N/C O2O4O6O8GND VDDO1 O3 O5 O7 O9 O10 3D7220-xx DIP 3D7220G-xx Gull-Wing 12345678161514131211109IN N/C N/C O2O4O6O8GNDVDD N/C O1 O3 O5 O7 O9 O103D7220S-xx SOL1234567141312111098IN N/C O2O4O6O8GND VDD O1 O3 O5 O7 O9 O103D7220D-xx SOIC PIN DESCRIPTIONS IN Delay Line Input O1 Tap 1 Output (10%) O2 Tap 2 Output (20%) O3 Tap 3 Output (30%) O4 Tap 4 Output (40%) O5 Tap 5 Output (50%) O6 Tap 6 Output (60%) O7 Tap 7 Output (70%) O8 Tap 8 Output (80%) O9 Tap 9 Output (90%) O10 Tap 10 Output (100%) VDD +5 Volts GND Ground TABLE 1: PART NUMBER SPECIFICATIONS TOLERANCES INPUT RESTRICTIONS DASH NUMBER TOTAL DELAY (ns) TAP-TAP DELAY (ns) Recd Max Frequency Absolute Max Frequency Recd Min Pulse Width Absolute Min Pulse Width-.75 6.75 0.5* 0.75 0.428.4 MHz 166.7 MHz 17.6 ns 3.00 ns -1 9.0 0.5* 1.0 0.523.8 MHz 166.7 MHz 21.0 ns 3.00 ns -1.5 13.5 0.5* 1.5 0.718.0 MHz 166.7 MHz 27.8 ns 3.00 ns -2 18.0 0.5* 2.0 0.814.5 MHz 166.7 MHz 34.5 ns 3.00 ns -2.5 22.5 0.5* 2.5 1.012.1 MHz 125.0 MHz 41.2 ns 4.00 ns -4 36.0 0.7* 4.0 1.38.33 MHz 133.3 MHz 60.0 ns 6.00 ns -5 50.0 1.0 5.0 1.56.67 MHz 66.7 MHz 75.0 ns7.50 ns -10 100.0 2.0 10.0 2.03.33 MHz 33.3 MHz 150 ns 15.0 ns -20 200.0 4.0 20.0 4.01.67 MHz 16.7 MHz 300 ns 30.0 ns -50 500.0 10 50.0 100.67 MHz 6.67 MHz 750 ns 75.0 ns -100 1000 20 100 200.33 MHz 3.33 MHz 1500 ns 150 ns -7007000 140 700 1400.05 MHz 0.48 MHz 10500 ns 1050 ns* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns 1.0nsNOTE: Any dash number between .75 and 700 not shown is also available as standard.2005 Data Delay DevicesAPPLICATION NOTES OPERATIONAL DESCRIPTION The 3D7220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series.Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.INPUT SIGNAL CHARACTERISTICS The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.OPERATING FREQUENCY The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7220 must be tested at the user operating frequency.Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. Theprogrammed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay