西北工业大学硬件描述语言语与 FPGA实验报告学院学号姓名专业实验时间实验地点指导教师西北工业大学20 年 月利用状态机实现比较复杂的接口设计一、实验目的及要求1. 学习运用由状态机控制的逻辑开关，设计出一个比较复杂的接口逻辑;2. 在复杂设计中使用任务(task)结构，以提高程序的可读性；3. 加深对可综合风格模块的认识。二、实验设备(环境)及要求预装了开发工具synplify、ModelSimSE的PC机。三、实验内容与步骤内容：利用状态机实现一个比较复杂的接口设计。步骤：1.建立工程并编写模块源码；2.编写测试模块并思考状态机是如何实现复杂的接口设计的；3布局布线并仿真；4. 记录数据并完成实验报告。四、实验代码module writing(reset,clk,address,data,sda,ack);input reset, clk;input7:0 data, address;inout sda;output ack;reg link_write;reg3:0 state;reg4:0 sh8out_state;reg7:0 sh8out_buf;reg finish_F;reg ack;parameter idle=0,addr_write=l,data_write=2,stop_ack=3;parameter bit0=1,bit1=2,bit2=3,bit3=4,bit4=5,bit5=6,bit6=7,bit7=8;assign sda=link_write ? sh8out_buf7: 1bz;always (posedge clk)begin if(!reset) begin link_write =0; state=idle;finish_F=0;sh8out_state =idle; ack=0;sh8out_buf =0;endelsecase(state)idle:beginlink_write =0;finish_F=0;sh8out_statev=idle;ack=0;sh8out_buf =address; state=addr_write;endaddr_write:begin if(finish_F=O) begin shift8_out;endelsebeginsh8out_state = idle; sh8out_buf = data; state=data_write; finish_F=0;endenddata write:beginif(finish_F=O)begin shift8_out; end elsebegin link_writev=O; state= stop_ack; finish_F=0; ack=1;endendstop_ack: begin ack=0; statev=idle;endendcaseendtask shift8_out;begincase(sh8out_state)idle:beginlink_writev=l; sh8out_statev=bit7;endbit7:beginlink_write=1; sh8out_statev=bit6;sh8out_bufv=sh8out_bufvv1; endbit6:beginsh8out_statev=bit5; sh8out_bufv=sh8out_bufvv1;endbit5:beginsh8out_statev=bit4;sh8out bufv=sh8out bufvv1;endbit4: beginsh8out_statev=bit3; sh8out_bufv=sh8out_bufvvl; endbit3: beginsh8out_statev=bit2; sh8out_bufv=sh8out_bufvv1; endbit2: beginsh8out_statev=bit1; sh8out_bufv=sh8out_bufvv1; endbitl: beginsh8out_statev=bitO; sh8out_bufv=sh8out_bufvv1; endbit0: beginlink_writev=O; finish_F=1;endendcaseendendtaskendmodule测试代码.timescale 1ns/100ps define clk_cycle 50 module writingTop;reg reset,clk; reg7:0data,address; wire ack,sda;always #clk cycle clk =clk;initialbeginclk=O;reset=l;data=0;address=O;#(2*clk_cycle) reset=0;#(2*clk_cycle) reset=1;#(100*clk_cycle) $stop;endalways(posedge ack)begindata=data+1;address=address+1;endwritingwriting(.reset(reset),.clk(clk),.data(data),.address(address),.ack(ack),.sda(sda); endmodule五、仿真综合结果仿真图综合图RTL级网表n_state_4 nSh_F_2_sqmwQ门级网标六、教师评语成绩签名:日期: