金属-绝缘层-半导体接触系统之综合研究暨此系统于n型砷化铟镓半导体基板之应用Comprehensive study on M-I-S contact system and its application to n-InGaAs semiconductor substrate 摘要本篇论文着重在III-V族化合物半导体材料砷化铟镓(InGaAs)金属-绝缘层-半导体(M-I-S)接触系统之研究，随着硅基元件逐渐面临了其发展的瓶颈，III-V族化合物半导体因此被视为是下一个世代n型晶体管通道的替代材料。其原因主要是因为III-V族化合物拥有较高的电子迁移率以及较低的等效电子质量。然而像硅、锗等材料一样，III-V族化合物的金属-半导体接面也有所谓费米能阶钉扎(Fermi Level Pinning)的现象。近期，学者们提出在金属与半导体之间嵌入一极薄的绝缘层(Insulator)，可以减缓费米能阶钉扎，调变萧特基能障(Schottky Barrier Height)，越低萧特基能障可以获得更低的接触电阻，对于目前小线宽元件的效能，特别是在导通状态时的电流，可以有大幅提升的机会。故M-I-S接触系统亦是目前半导体领域正火热的一个议题。第一部分我收集了目前M-I-S系统之发展进程，并列举出一些不同种类半导体，如：硅、锗与III-V族半导体以M-I-S接触系统作为研究主轴的论文，对于M-I-S接触系统的主要机制：费米能阶解钉扎也给予了一些理论描述，而对于M-I-S接触系统降低电阻值的机制，我有也稍作定性的描述，其关键来自于插入之绝缘层性质(如：介电系数(dielectric constant)、能带位移(band offset)、载子等效质量(carrier effective mass)、能隙(band gap)等)与基板交互作用产生的影响。第二部分我以III-V族半导体基板：砷化铟镓，并搭配三种不同种类之绝缘层：钛酸钡(BaTiO3)、二氧化钛(TiO2)及氧化锌(ZnO)，并使用钛作为接触金属，实际做出M-I-S接触结构，量测其接触电阻，并将此实验结果与M-S接触的样品做比较，发现当插入之绝缘层为氧化锌时，其接触电阻值会比原本没有绝缘层之样品小约10倍，我们发现氧化锌与砷化铟镓基板的传导带位移(Conduction Band Offset)接近零，即使其介电系数大小与其他二绝缘层相比不是很高，仍可以达到降低接触电阻值的效果。关键字：砷化铟镓、接触电阻、萧特基能障、费米能阶钉札、金属-绝缘层-半导体接触系统Abstract In this paper, we make a comprehensive study on Metal-Insulator-Semiconductor (M-I-S) contact system for III-V compound material, InGaAs. With the scaling limitation of Si-based device, III-V compound materials are regarded as the promising candidates for n-channel device in next generation because of its high electron mobility and low electron effective mass. However, III-V compound materials also have the same problem as Si or Ge, the Fermi Level Pinning (FLP). Recently, the Metal-Insulator-Semiconductor (M-I-S) contact structures have been proposed to release the Fermi Level Pinning (FLP), by modulating the Schottky Barrier Height (SBH) and futher reduce the contact resistivity. Reduction of contact resistivity plays an important role on boosting the device performance, especially in on-state current, in scaling generation. At the first part, I collect several literatures about recent M-I-S development and list some papers which focus on M-I-S contact system based on different semiconductor substrates i.e. Si, Ge and III-V compound material. Then the mechanisms of Fermi Level Pinning and M-I-S contact system are also given. The key points of reduction of contact resistivity using M-I-S system are the properties of inserting insulator i.e. dielectric constant, band offset, carrier effective mass and band gap as well as the interactions between insulator and substrate. At the second part, I use three different kinds of insulator: BaTiO3, TiO2 and ZnO on InGaAs substrate. Then Ti is used as contact metal to form M-I-S ohmic contact. The experimental results of M-S and M-I-S contact were discussed here. We find that the contact resistivity will reduce 10x when we insert ZnO as insulator. Due to its nearly zero conduction band offset, the reduction of contact resistivity is still achieved even though its dielectric constant is not high compare to other two insulators. Keywords: InGaAs, contact resistivity, Schottky Barrier Height, Fermi Level Pinning, Metal-Insulator-Semiconductor contact system目录口试委员审定书I摘要IIAbstractIII目录V图目录VII表目录XII1.1 半导体元件在尺度微缩下所面临的挑战11.2 新兴半导体技术演进41.3 III-V族复合半导体之兴起61.4源极与汲极之设计在奈米尺度下所面临的挑战91.5论文架构111.6 References12二、现今源/汲极电阻改善技术以及文献回顾132.1常见之源/汲极阻值改良方法132.2 M-I-S结构的提出以及其应用162.2.1费米能阶钉扎(Fermi level pinning)162.2.2如何使用M-I-S接触调变萧特基能障并降低接触电阻值192.2.3载子穿隧222.2.4 M-I-S氧化层选用之特性分析252.2.5 硅M-I-S结构的文献回顾272.2.6 锗M-I-S结构的文献回顾312.2.7 III-V族半导体M-I-S结构的文献回顾372.2.8 M-I-S一般性理论模型422.3 References48三、砷化铟镓M-I-S接触之萧特基能障暨接触电阻研究553.1简介553.2常见之萧特基能障及接触电阻量测手法553.2.1 传输线模型(Transmission Line Method TLM)553.2.2圆形传输线模型(Circular Transmission Line Method CTLM)583.2.3侧壁传输线模型(Sidewall Transmission Line Method STLM)593.2.4四点交叉电桥凯尔文量测(Four Terminal Cross-Bridge Kelvin 4T-CBK)623.2.5精细传输线模型(Refined Transmission Line Method RTLM)633.2.6萧特基能障之量测653.3 n型砷化铟镓M-I-S接触制程概述693.3.1晶圆结构介绍693.3.2制程步骤及制程参数713.4 n型砷化铟镓M-S与M-I-S接触实验量测结果与讨论723.5 References78四、总结与未来展望804.1总结804.2未来展望82图目录图1.1芯片上的晶体管数量与年份的对应函数21图1.2藉由引进多核心运算，原本近乎指数成长的CPU功率密度将可被平缓32图1.3 45-nm节点后芯片效能、功耗与单位瓦数的效能之变化示意图122图1.4 传统硅基MOSFET示意图63图1.5 在尺度微缩下微处理器之驱动功率与漏电功率24图1.6 至22-nm半导体各个技术节点之演进撷取自Intels technology roadmap 20125图1.7 22-nm后三维晶体管未来之走向撷取自Apply Material6图1.8传统长通道载子传输与短通道弹道传输与饱和电流之关系，无论是在载子迁移率或是射出速度，III-V族复合材料都具有优势8图1.9 III-V族复合半导体与硅的射出速度(vinj)比较58图1.10 平面晶体管各电阻分量示意图89图1.11a Intel 22-nm节点寄生电阻各个分量所占的比例910图1.11b 平面CMOS寄生与通道电阻对技术节点之关系1010图1.11c 接触电阻增加百分比与元件延迟增加百分比之关系1211图2.1 根据ITRS，在微缩趋势下，物理闸极线宽以及源/汲极接面深度之关系13图2.2各种退火方式的退火温度与时间关系1415图2.3界面(缺陷)能态示意图16图2.4半导体晶格表面的悬浮键撷取自pveducation.org17图2.5 n型锗、硅和砷化镓铟的CNL2017图2.6 n型锗半导体的萧特基能障对金属功函数之关系2019图2.7 M-I-S系统调变萧特基能障之示意图21图2.8 M-I-S接触电阻值之权衡(trade-off)21图2.9不同能隙半导体之复数能带图1926图2.10常见氧化层材料的能带与介电系数关系26图2.11常见半导体材料的能隙与钉扎因子关系(模拟与实验)