杭电计组实验-实现R型指令的CPU设计实验作者:日期:#实验报告姓名阳光男学号16041321班级16052317专业计算机科学与技术课程名称计算机组成原理与系统结构试 验任课老师张翔老师指导老师张翔老师机位号无实验序号8实验名 称实验八 实现R型指令的CPU设计实验实验时间2018/5/25实验地占八、1 教 225实验设备 号个人电脑一、实验程序源代码顶层LED测试模块：module Top_LED(clk,rst,SW,LED);in put clk,rst;in put 2:0SW;output reg7:0LED;wire ZF,OF;wire 31:0ALU_F;top_R_cpu test_cpu(rst,clk,ZF,OF,ALU_F); always(*)begi ncase(SW)3b000:L ED=ALU_F7:0;3b001:LED=ALU_F15:8;3b010:LED=ALU_F23:16;3b011:LED=ALU_F31:24;3b100:begin LED7:2=0;LED1=0F;LED0=ZF;e nd default:LED=0;endcaseend2018年_6_月 1 日成绩：en dmodule顶层R型CPU模块：module top_R_cpu(input rst,input clk,output ZF,output OF,output 31:0F); reg write_reg;wire 31:0l nst_code;wire 31:0R_Data_A;wire 31:0R_Data_B;reg 2:0ALU_OP;pc pc_c onn ect(clk,rst,I nst_code);Register_file R_co nn ect(I nst_code25:21,l nst_code20:16,In st_code15:11,write_reg,F,clk,rst, R_Data_A,R_Data_B);ALU ALU_co nn ect(R_Data_A,R_Data_B,F,ALU_OPOF);always(*)begi nwrite_reg=0;ALU_OP=0;if(I nst_code31:26=0)begi ncase(I nst_code5:0)6b100000:ALU_OP=3b100;6b100010:ALU_OP=3b101;6b100100:ALU_OP=3b000;6b100101:ALU_OP=3b001;6b100110:ALU_OP=3b010;6b100111:ALU_OP=3b011;6b101011:ALU_OP=3b110;6b000100:ALU_OP=3b111;endcasewrite_reg=1;endenden dmodulePC取指令模块：module pc(i nput clk,i nput rst,output 31:0l nst_code); reg 31:0PC;wire31:0PC_ new;in itialPC=32h00000000;In st_ROM In st_ROM1 (.clka(clk),.addra(PC7:2),.douta(I nst_code);assign PC_n ew二24h000000,PC_ new7:0; always (n egedge clk or posedge rst) begi nif(rst)PC=32h00000000;else PC=PC_new;enden dmodule寄存器堆模块:moduleB);Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data in put 4:0R_Addr_A;in put 4:0R_Addr_B;in put 4:0W_Addr;in put Write_Reg;in put 31:0W_Data;in put Clk;in put Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;#initial/仿真过程中的初始化begi nfor(i=0;iv=31;i二i+1)REG_Filesi=O;endassign R_Data_A=REG_FilesR_Addr_A; assign R_Data_B=REG_FilesR_Addr_B; always(posedge Clk or posedge Reset) begi nif(Reset)for(i=0;i=31;i=i+1)REG_Filesi=O;elseif(Write_Reg&W_Addr!=0)REG_FilesW_Addr=W_Data;enden dmoduleALU算术逻辑运算单元模块：module ALU(A,B,F,ALU_QZF,OF);in put 31:0A,B;in put 2:0ALU_OP;output reg ZF,OF;output reg31:0F;reg C32;always(*)begi nOF=1b0;C32=1b0;case(ALU_OP)3b000:F=A&B;3b001:F=A|B;3b010:F=AAB;3bO11:F=(AB);3b100:begin C32,F=A+B;OF=A31AB31AF31AC32;e nd3b101:begin C32,F二A-B;OF二A31AB31AF31FC32;e nd 3b110:if(AB)F=1;elseF=0;3b111:F=B A;endcaseif(F=0)ZF=1;elseZF=0;enden dmodule测试代码：module test;/In putsreg rst;reg clk;/ Outputswire ZF;wire OF;wire 31:0 F;/ I nsta ntiate the Unit Under Test (UUT) top_R_cpu uut (.rst(rst),.clk(clk),ZF(ZF),.OF(OF),F(F)；in itial beg in/I nitialize In putsrst = 0;clk = 0;/ Wait 100 ns for global reset to finish#100;clk=1;/ Add stimulus here forever beg in#50; clk=clk;endend en dmodule二、仿真波形#构:三、电路图顶层电路模块SW（2:0toppledLED（7：0）elkretTop_LEDTop_LED顶层电路内部结四、引脚配置（约束文件）NET LED7 LOC :=T11;NET LED6 LOC :=R11;NET LED5 LOC :=N11;NET LED4 LOC =M11;NET LED3 LOC :=V15;NET LED2 LOC :=U15;NET LED1 LOC :=V16;NET LED0 LOC :=U16;NET SW2 LOC=V9;NET SW1 LOC=T9;NET SW0 LOC :=T10;NET clk LOC =C9;NET rst LOC =C4;五、思考与探索(1)R型指令CPU实验结果记录表序号指令执行结果标志结论10000827FFFFFFFF00正确20001102b0000_000100正确3004218200000_000200正确4006220200000_000300正确5008328200000_000500正确600a330200000_000700正确7004638040000_000E00正确800a648200000_000C00正确9012640040000_700000正确1000284826FFFF_8FFF00正确1101215020FFFF_8FFE00正确12010758220000_6FF200正确1300e86022FFFF_900E00正确14012c6824FFFF_800E00正确15012c7025FFFF_9FFF00正确1600c778250000_FFFF正确