module charlcd1(clk,reset,lcd_rs,lcd_rw,lcd_e,data,clk_out);input clk,reset;output reg lcd_rs,lcd_rw;output wire clk_out;output reg lcd_e;output reg 7:0 data;parameter 10:0 idle =11b00000000000;parameter 10:0 clear =11b00000000001;parameter 10:0 returncursor=11b00000000010;parameter 10:0 setmode =11b00000000100;parameter 10:0 switchmode =11b00000001000;parameter 10:0 shift =11b00000010000;parameter 10:0 setfunction =11b00000100000;parameter 10:0 setcgram =11b00001000000;parameter 10:0 setddram =11b00010000000;parameter 10:0 readflag =11b00100000000;parameter 10:0 writeram =11b01000000000;parameter 10:0 readram =11b10000000000;parameter cur_inc =1;parameter cur_dec =0;parameter cur_shift =1;parameter cur_noshift =0;parameter open_display =1;parameter open_cur =0;parameter blank_cur =0;parameter shift_display=1;parameter shift_cur =0;parameter right_shift =1;parameter left_shift =0;parameter datawidth8 =1;parameter datawidth4 =0;parameter twoline =1;parameter oneline =0;parameter font5x10 =1;parameter font5x7 =0;reg 10:0 state;reg 6:0 counter;reg 3:0 div_counter;reg flag;parameter divss=15;reg 5:0 char_addr;/reg 7:0 data_in;wire 7:0 data_in;/时钟信号clkdiv的相关变量定reg clk_int;reg 18:0 clkcnt;parameter divcnt=19b1111001110001000000;reg clkdiv;reg tc_clkcnt;/产生时钟信号clkdivalways(posedge clk or negedge reset)beginif(reset=0) begin clkcnt=0;tc_clkcnt=0; /重置 end else if(clkcnt=divcnt) begin clkcnt=0;tc_clkcnt=1; /每计数到x79c40,to_clkcnt赋予高电平 endelse begin clkcnt=clkcnt+1;tc_clkcnt=0; endend/clkdiv是以2倍的x79c40为周期的时钟信号 always(posedge tc_clkcnt or negedge reset)beginif(reset=0) clkdiv=0;else clkdiv=clkdiv;end/产生周期为clkdiv的2倍的时钟信号clk_int,并赋给clk_outassign clk_out=clk_int;always(posedge clkdiv or negedge reset)beginif(reset=0) clk_int=0;else clk_int=clk_int;end/产生周期为clkdiv的2倍的时钟信号lcd_e,与clk_int相错90always(negedge clkdiv or negedge reset)beginif(reset=0) lcd_e=0;else lcd_e=lcd_e;end/*调用char_ram元件*/char_ram aa(clk,char_addr,data_in);/*/always(posedge clk)beginif(state=writeram) lcd_rs=1;else if(state=readram) lcd_rs=1;else lcd_rs=0;endalways(posedge clk)beginif(state=idle) lcd_rw=1;else if(state=readram) lcd_rw=1;else lcd_rw=0;endalways(posedge clk)begincase(state) /各状态下，给data赋值，完成拼接工作clear: data=8b00000001;returncursor: data=8b00000010;setmode: data=8b00000110;/6b000001,cur_inc,cur_noshift;也可以用双斜线后面的写法，我当时为了自己方便看就直接写了出来switchmode: data=8b00001100;/5b00001,open_display,open_cur,blank_cur;shift: data=8b00011000;/4b0001,shift_display,left_shift,2b00;setfunction: data=8b00111100;/3b001,datawidth8,twoline,font5x10,2b00;setcgram: data=8b01000000;setddram:begin if(counter=0) data=8b10000000; else data=8b11000000; endwriteram: data=data_in;default: data=8bzzzzzzzz;endcaseendalways(posedge clk)beginif(state=writeram) if(counter40) char_addr40 & counter73) char_addr73 & counter81) char_addr=counter-73; else char_addr=0;end/*/always(posedge clk_int or negedge reset)beginif(reset=0) begin state=idle; counter=0; flag=0; div_counter=0; endelse case(state) idle:begin if(flag=0) begin state=setfunction; flag=1; counter=0; div_counter=0; end else if(div_counterdivss) begin div_counter=div_counter+1; state=idle; end else begin div_counter=0; state=shift; end end clear: state=setmode; setmode: state=writeram;/ returncursor: state=writeram; switchmode: state=clear; shift: state=idle; setfunction: state=switchmode;/ setcgram: state=idle; setddram: state=writeram;/ readflag: state=idle; writeram:begin if(counter40) begin state=writeram; counter=counter+1; end else if(counter=40) begin state=setddram; counter=counter+1; end else if(counter81) begin state=writeram; counter=counter+1; end else state=shift; end/ readram: state=idle;/ default: state=idle; endcaseendendmodule （2） module char_ram(clk,address,data);input clk;input 5:0 address;output reg 7:0 data;/*这里注释掉的因为我一直没用对，还在学习中，有人知道的吗？请多多指教function 7:0 char_to_integer;input indata;begincase(indata)