序列发生器设计序列发生器设计 (2)序列发生器序列发生器数字系统中，常需要串行周期性信号；序列信号：按照特定顺序排列的串行数字信号；序列信号发生器：生成某个特定规则下的序列信号的电路。2序列发生器的功能仿真波形的建立序列发生器的功能仿真波形的建立9计数型序列信号发生器计数型序列信号发生器以同步计数器为基础；例：设计产生序列信号为1111000100的发生器；序列长度M=10，选用一个模10的同步计数器10计数型序列信号发生器计数型序列信号发生器Q3Q2Q1Q0F00001000110010100111010000101001100011111000010010F=(not(Q3)and not(Q2) or (Q1 and Q0)11计数型序列信号发生器计数型序列信号发生器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counterxuelie isport(clk:in std_logic; clr: in std_logic; f:out std_logic; q:out std_logic_vector(3 downto 0);end counterxuelie;architecture behavioral of counterxuelie issignal q0:std_logic_vector(3 downto 0);signal temp1,temp2,temp3:std_logic;beginprocess(clk,clr)beginif(clr=0)thenq0=0000;elsif(clkevent and clk=1)thenif(q0=1001)thenq0=0000;elseq0=q0+1;end if;end if;end process;q=q0;temp1=(not q0(3)and (not q0(2);temp2=q0(1) and q0(0);temp3=(not temp1) and (not temp2);f state = S1 ; current_state state = S2 ; current_state state = S3; current_statestate = S4;current_statestate = S5;current_statestate = S6; current_statestate = S0; current_state state = S1; end case; END IF; end process;end Behavioral;15状态图状态图利用利用QuartusII软件软件16