Faculty of Materials and Energy, Guangdong University of TechnologyReview2024/9/82.1 Threshold voltageDigital Integrated CircuitsFaculty of Materials and Energy, GDUT22024/9/84.1 CMOS inverter-1Digital Integrated CircuitsFaculty of Materials and Energy, GDUT3截止线性VDD+VTPVi VDD饱和线性VO+VTNViVDD+VTP饱和饱和VO+VTPViVO+VTN线性饱和VTNViVO+VTP线性截止0ViVTNP管N管输入电压范围2024/9/84.1 CMOS inverter-2vVOHvVOLvVIHvVILvVSvNML、NMHv以及各点相对应的VoutDigital Integrated CircuitsFaculty of Materials and Energy, GDUT42024/9/84.2 Other invertersvNMOS inverters with resistive load or NMOS loadvPseudo invertersvStructure、VOL、VOH、VIL、VIHvDelay time: 0.7RCvReqn=12.5K；Reqp=30KvInverter SizeDigital Integrated CircuitsFaculty of Materials and Energy, GDUT52024/9/85.1 Static MOS gate circuitsv逻辑表达式电路v尺寸选择Digital Integrated CircuitsFaculty of Materials and Energy, GDUT62024/9/85.2 Static MOS gate circuits v尺寸选择：延时v尺寸选择：VOLvCMOS电路中只需要考虑延时Digital Integrated CircuitsFaculty of Materials and Energy, GDUT72024/9/85.3 Static MOS gate circuits vS到Q的延时为一个与非门的延时vS到Q非的延时为2个与非门的延时Digital Integrated CircuitsFaculty of Materials and Energy, GDUT82024/9/86.1 逻辑强度Digital Integrated CircuitsFaculty of Materials and Energy, GDUT92024/9/86.2 寄生参数项Digital Integrated CircuitsFaculty of Materials and Energy, GDUT10v门的寄生参数项与工艺及门、版图有关v反相器的寄生参数项P为：vP与结电容、门电容的系数有关v二输入与非门为：v二输入或非门为：v多输入门的P可近似为表6.22024/9/86.3 用逻辑强度优化路径Digital Integrated CircuitsFaculty of Materials and Energy, GDUT11v逻辑强度：LEP=(4/3)3v电学强度：FOP=Cout/Cin=4.5v分支强度：BEP=2*3=6v路径强度：PE=64v最优化的级强度：SE*=(PE)1/3=4v延时：D=3*4+3*1=15v反向计算门尺寸：vCin=LE*BE*Cout/SE*vZ=1*4.5*(4/3)/4=1.5vY=3*1.5*(4/3)/4=1.5vX=2*1.5*(4/3)/4=12024/9/8考点v计算题：4/69v版图题：1/10v逻辑电路：3/21Digital Integrated CircuitsFaculty of Materials and Energy, GDUT122024/9/8现代科学技术导论现代科学技术导论广东工业大学微电子材料与工程系广东工业大学微电子材料与工程系1313