9.2 乘法器设计n 应用 数字信号处理和数字通信n 地位 影响系统的运行速度n 实现l 并行乘法器l 移位相加乘法器l 查找表乘法器l 加法树乘法器2021/3/101讲解：XX9.2.1 并行乘法器l 结构 用乘法运算符描述 由EDA软件综合l 优点 运算速度快l 缺点 耗用资源多2021/3/102讲解：XX【例9.4】8位并行乘法器module mult( outcome, a, b);parameter size = 8;inputsize:1 a, b; / 源操作数output2*size:1 outcome; / 乘积assign outcome = a*b; / 相乘endmodule2021/3/103讲解：XX8位并行乘法器RTL图2021/3/104讲解：XX9.2.2 移位相加乘法器l 结构 移位寄存器 加法器l 优点 耗用资源少2021/3/105讲解：XX【例9.16】8位二进制数的乘法module mult_for( outcome, a, b );parameter size = 8;inputsize:1 a, b;output2*size:1 outcome;reg2*size:1 outcome;integer i;2021/3/106讲解：XXalways ( a or b )begin outcome = 4h0;for( i = 1; i = size; i = i+1 ) if( bi ) outcome = outcome + ( a (i-1) );endendmodule2021/3/107讲解：XX乘法器的功能仿真波形图2021/3/108讲解：XX9.2.3 查找表乘法器l 结构 操作数：地址 乘积：存储器l 优点 运算速度快l 缺点 耗用存储资源多2021/3/109讲解：XXl 设计思路n 4位查找表乘法器 Y = AB A = A122+A2 B = B122+B2 则 Y = ( A122+A2 )( B122+B2 ) = A1B124 + A1B222 + A2B122 + A2B22021/3/1010讲解：XXn 8位查找表乘法器 Y = AB A = A124+A2 B = B124+B2 则 Y = ( A124+A2 )( B124+B2 ) = A1B128 + A1B224 + A2B124 + A2B22021/3/1011讲解：XX【例9.5】 88查找表乘法器/* 22查找表乘法器 */module lookup( out, a, b, clk );output3:0 out; / 乘积input1:0 a, b; / 操作数input clk;reg3:0 out;reg3:0 address; / 存储器地址2021/3/1012讲解：XXalways ( posedge clk )beginaddress = a, b ;case( address )4h0:out = 4b0000;4h1:out = 4b0000;4h2:out = 4b0000;4h3:out = 4b0000;4h4:out = 4b0000;4h5:out = 4b0001;4h6:out = 4b0010;4h7:out = 4b009;2021/3/1013讲解：XX4h8:out = 4b0000;4h9:out = 4b0010;4ha:out = 4b0100;4hb:out = 4b090;4hc:out = 4b0000;4hd:out = 4b009;4he:out = 4b090;4hf:out = 4b1001;default: out = 4bx;endcaseendendmodule2021/3/1014讲解：XX/* 44查找表乘法器 */module mult4x4( out, a, b, clk );output7:0 out; / 乘积input3:0 a, b; / 操作数input clk;reg7:0 out;reg1:0 firsta, firstb; / 操作数高2位reg1:0 seconda, secondb; / 操作数低2位wire3:0 outa, outb, outc, outd; / 乘积每2位1组2021/3/1015讲解：XXalways ( posedge clk )beginfirsta = a3:2;seconda = a1:0;firstb = b3:2;secondb = b1:0;end2021/3/1016讲解：XXlookup m1( outa, firsta, firstb, clk ), / 元件调用 m2( outb, firsta, secondb, clk ), m3( outc, seconda, firstb, clk ), m4( outd, seconda, secondb, clk );always ( posedge clk )beginout = ( outa 4 ) + ( outb 2 ) / 乘积 + ( outc 2 ) + outd;endendmodule2021/3/1017讲解：XX4位查找表乘法器仿真波形图2021/3/1018讲解：XX/* 88查找表乘法器 */module mult8x8( out, a, b, clk );output15:0 out; / 乘积input7:0 a, b; / 操作数input clk;reg15:0 out;reg3:0 firsta, firstb; / 操作数高4位reg3:0 seconda, secondb; / 操作数低4位wire7:0 outa, outb, outc, outd; / 乘积每8位1组2021/3/1019讲解：XXalways ( posedge clk )beginfirsta = a7:4;seconda = a3:0;firstb = b7:4;secondb = b3:0;end2021/3/1020讲解：XXmult4x4 n1( outa, firsta, firstb, clk ), / 元件调用 n2( outb, firsta, secondb, clk ), n3( outc, seconda, firstb, clk ), n4( outd, seconda, secondb, clk );always ( posedge clk )beginout = ( outa 8 ) + ( outb 4 ) / 乘积 + ( outc 4 ) + outd;endendmodule2021/3/1021讲解：XX8位查找表乘法器仿真波形图2021/3/1022讲解：XX9.2.4 加法树乘法器l 结构 底层：乘法器 高层：多级加法器l 优点 1个时钟周期完成2021/3/1023讲解：XX加法树乘法器结构框图81乘法器a128b781乘法器a64b6加法器81乘法器a32b581乘法器a16b4加法器81乘法器a8b381乘法器a4b2加法器81乘法器a2b181乘法器ab0加法器加法器加法器加法器y=ab2021/3/1024讲解：XX【例9.6】8位加法树乘法器module add_tree( out, a, b, clk );output15:0 out; / 乘积input7:0 a, b; / 操作数input clk;wire15:0 out;wire15:0 out1, c1; / 加法器和wire13:0 out2;wire11:0 out3, c2;wire9:0 out4;2021/3/1025讲解：XXreg14:0 temp0; / 最高位乘积reg13:0 temp1;reg12:0 temp2;reg11:0 temp3;reg10:0 temp4;reg9:0 temp5;reg8:0 temp6;reg7:0 temp7; / 最低位乘积2021/3/1026讲解：XX/* 81乘法器 */function7:0 mult8x1;input7:0 operand;input sel;beginmult8x1 = ( sel ) ? ( operand ) : 8b00000000;endendfunction2021/3/1027讲解：XX/* 操作数b各位与操作数a相乘 */always ( posedge clk )begintemp7 = mult8x1( a, b0 );temp6 = ( mult8x1( a, b1 ) ) 1;temp5 = ( mult8x1( a, b2 ) ) 2;temp4 = ( mult8x1( a, b3 ) ) 3;temp3 = ( mult8x1( a, b4 ) ) 4;temp2 = ( mult8x1( a, b5 ) ) 5;temp1 = ( mult8x1( a, b6 ) ) 6;temp0 = ( mult8x1( a, b7 ) ) 7;end2021/3/1028讲解：XX/* 加法器树运算 */assign out1 = temp0 + temp1;assign out2 = temp2 + temp3;assign out3 = temp4 + temp5;assign out4 = temp6 + temp7;assign c1 = out1 + out2;assign c2 = out3 + out4;assign out = c1 + c2;endmodule2021/3/1029讲解：XX8位加法树乘法器仿真波形图2021/3/1030讲解：XX四种乘法器的比较2021/3/1031讲解：XX9.3 乘累加器（MAC）的设计 2021/3/1032讲解：XX【例9.30】乘累加器（MAC）module MAC( out, opa, opb, clk, clr );output15:0 out;input7:0 opa, opb;input clk, clr;wire15:0 sum;reg15:0 out;2021/3/1033讲解：XXfunction15:0 mult;input7:0 opa, opb;reg 15:0 result;integer i;begin result = opa0 ? opb : 0; for(i = 1; i = 7; i = i+1)begin if( opai = 1 ) result = result + ( opb (i-1) );end mult = result;endendfunction2021/3/1034讲解：XXassign sum = mult( opa, opb ) + out;always ( posedge clk or posedge clr )beginif( clr ) out = 0;else out = sum;end endmodule2021/3/1035讲解：XX感谢您的阅读收藏，谢谢！2021/3/1036