嵌入式系统设计与应用嵌入式系统设计与应用STM32F103MCU本课程的主要内容本课程的主要内容Embedded System Interface Design and Application信息信息学院学院主要内容主要内容nCortex-M3的的总结总结nSTM32F系列的特点系列的特点nSTM32F103系列的特点系列的特点nSTM32F103的概述的概述nSTM32F103的外特性的外特性nSTM32F103的内特性的内特性nSTM32F103的的SFRnSTM32F103的的应应用用Embedded System Interface Design and Application信息信息学院学院主要参考资料主要参考资料nSTM32F103xxx_Datasheet.pdfnSTM32F103xxx_Reference_Manual.pdfnSTM32F103xxx_Library_Manual.pdfnRVMDK 3.2Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的总结总结uCM3uNVICuEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uCortex-M3 block diagramEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelARMv7-M architecture. The main features:Thumb-2 instruction set subset.Harvard Architecture with data load/store.Three-stage pipeline.Single cycle 32-bit multiply.Hardware divide.Thumb and Debug states.Handler modes and Thread modes.without the overhead of state saving and restoration between interrupts.Interruptible-continued LDM/STM, PUSH/POP.ARMv6 compatible BE8 and LE access support.ARMv6 compatible unaligned access support.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelARMv7-M architecture. The main features:Low latency ISR entry and exit.Processor state saving and restoration, with no instruction fetch overhead. Exception vector is fetched from memory in parallel with the state saving, enabling faster ISR entry. Support for late arriving (迟来迟来) interrupts. Tightly coupled interface to interrupt controller enabling efficient processing of late-arriving (迟迟来来) interrupts. Tail-chaining(尾尾连连) of interrupts, enabling back-to-back(背靠背背靠背) interrupt processingEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelRegisters The processor contains:13 general purpose 32-bit registers, R0 to R12Link Register (LR)-R14Program Counter (PC) -R15Program Status Register, xPSRtwo banked SP registers. -R13Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelMemory interfaceThe processor has a Harvard interface to enable simultaneous instruction fetches with data load/stores. Memory accesses are controlled by:A separate Load Store Unit (LSU) that decouples load and store operations from the Arithmetic and Logic Unit (ALU).A 3-word entry Prefetch Unit (PFU). One word is fetched at a time. This can be two Thumb instructions:one word-aligned Thumb 32-bit instruction;the upper/lower halfword of a halfword-aligned Thumb 32-bit instruction with one Thumb instruction, or the lower/upper halfword of another halfword-aligned Thumb 32-bit instruction.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelNVICThe NVIC is tightly coupled to the processor core. This facilitates low latency exception processing. The main features include:a configurable number of external interrupts, from 1 to 240a configurable number of bits of priority, from three to eight bitslevel and pulse interrupt supportdynamic reprioritization of interruptspriority groupingsupport for tail-chaining of interruptsprocessor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelBus matrixThe bus matrix connects the processor and debug interface to the external buses. The bus matrix interfaces to the following external buses:ICode bus. This is for instruction and vector fetches from code space, it is a 32-bit AHB-Lite bus.DCode bus. This is for data load/stores and debug accesses to code space. it is a 32-bit AHB-Lite bus.System bus. This is for instruction and vector fetches, data LD/ST and debug accesses to system space. This is a 32-bit AHB-Lite bus.PPB. This is for data LD/ST and debug accesses to PPB space. This is a 32-bit APB (v3.0) bus.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelBus matrixThe bus matrix also controls the following:Unaligned accesses. The bus matrix converts unaligned processor accesses into aligned accesses.Bit-banding. The bus matrix converts bit-band alias accesses into bit-band region accesses. It performs: bit field extract for bit-band loads; atomic read-modify-write for bit-band stores.Write buffering. The bus matrix contains a one-entry write buffer to decouple bus stalls from the processor core.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelDWTYou can configure the implementation to include a DWT. If present, you can configure the DWT to incorporate the following debug functionality:four comparators that you can configure either as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data address sampler event triggerseveral counters or a data match event trigger for performance profiling(性能分析性能分析)configurable to emit PC samples at defined intervals, and to emit interrupt event information.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的特性的特性uProcessor corelETMYou can configure the system at implementation to include an ETM. This is a low-cost trace macrocell that supports instruction trace only.lWICYou can configure the implementation to include a Wake-up Interrupt Controller(WIC).Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uAbout the programmers modellThe processor architecture is the ARMv7-M. Instructions architecture is the Thumb-2.lOperating modes：The processor supports two modes of operation, Thread mode and Handler mode:Thread mode is entered on Reset, and can be entered as a result of an exception return. Privileged and User (Unprivileged) code can run in Thread mode.Handler mode is entered as a result of an exception. All code is privileged in Handler mode.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uAbout the programmers modellOperating statesThe processor can operate in one of two operating states:Thumb-2 state. This is normal execution running 16-bit and 32-bit halfword aligned Thumb instructions.Debug State. This is the state when in halting debug.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uPrivileged access and user accesslCode can execute as privileged or user: User(Unprivileged) execution limits or excludes access to some resources.Privileged execution has access to all resources.Handler mode is always privileged.Thread mode can be privileged or unprivileged.When Thread mode has been changed from privileged to user, it cannot change itself back to privileged.Only a Handler can change the privilege of Thread mode. Handler mode is always privileged.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uPrivileged access and user accesslMain stack and process stackOut of reset, all code uses the main stack. An exception handler such as SVC can change the stack used by Thread mode from main stack to process stack by changing the EXC_RETURN value it uses on exit. All exceptions continue to use the main stack. The stack pointer, r13, is a banked register that switches between SP_main and SP_process. Only one stack, the process stack or the main stack, is visible, using r13, at any time. It is also possible to switch from main stack to process stack while in Thread mode by writing to CONTROL1 using the MSR instruction, in addition to being selectable using the EXC_RETURN value from an exit from Handler mode.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslThe processor has the following 32-bit registers:13 general-purpose registers, r0-r12Stack point alias of banked registers, SP_process and SP_mainLink register, r14Program counter, r15One program status register, xPSR.Figure shows the processor register set.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslThe processor has the following 32-bit registers:13 general-purpose registers, r0-r12Stack point alias of banked registers, SP_process and SP_mainLink register, r14Program counter, r15One program status register, xPSR.Figure shows the processor register set.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslGeneral-purpose registersThe general-purpose registers r0-r12 have no special architecturally-defined uses. Most instructions that can specify a general-purpose register can specify r0-r12.Low registers Registers r0-r7 are accessible by all instructions that specify a general-purpose register.High registers Registers r8-r12 are accessible by all 32-bit instructions that specify a general-purpose register.Registers r8-r12 are not accessible by all 16-bit instructions.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslThe r13 have following special functions:Stack pointer Register r13 is used as the Stack Pointer (SP). Because the SP ignores writes to bits 1:0, it is autoaligned to a word, four-byte boundary.Handler mode always uses SP_main, but you can configure Thread mode to use either SP_main or SP_process.lThe r14 have following special functions:Link register Register r14 is the subroutine Link Register (LR).The LR receives the return address from PC when a Branch and Link (BL) or Branch and Link with Exchange (BLX) instruction is executed.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslThe r14 have following special functions:The LR is also used for exception return.At all other times, you can treat r14 as a general-purpose register.lThe r15 have following special functions:Program counter Register r15 is the Program Counter (PC).Bit 0 is always 0, so instructions are always aligned to word or halfword boundaries.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslSpecial-purpose Program Status Registers (xPSR)Processor status at the system level breaks down into three categories:Application PSRInterrupt PSRExecution PSRThey can be accessed as individual registers, a combination of any two from three, or a combination of all three using the Move to Register from Status (MRS) and MSR instructions.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslSpecial-purpose Program Status Registers (xPSR)Application PSRThe Application PSR (APSR) contains the condition code flags. Before entering an exception, the processor saves the condition code flags on the stack. You can access the APSR with the MSR(2) and MRS(2) instructions.Figure shows the bit assignments of the APSR.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSR APSREmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSRInterrupt PSRThe Interrupt PSR (IPSR) contains the Interrupt Service Routine (ISR) number of the current exception activation.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSR IPSREmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSR Execution PSRThe Execution PSR (EPSR) contains two overlapping fields:the Interruptible-Continuable Instruction(ICI) field for interrupted load multiple and store multiple instructions;the execution state field for the If-Then(IT) instruction, and the Thumb state bit (T-bit).Interruptible-continuable instruction field.Load Multiple(LDM) operations and Store Multiple (STM) operations are interruptible.The ICI field of the EPSR holds the information required to continue the load or store multiple from the point that the interrupt occurred.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSR Execution PSRIf-then state field:The IT field of the EPSR contain the execution state bits for the If-Then instruction.Because the ICI field and the IT field overlap, load or store multiples within an If-Then block cannot be interrupt-continued.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslxPSR EPSREmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uRegisterslSaved xPSR bitsOn entering an exception, the processor saves the combined information from the three status registers on the stack. The stacked xPSR also contains information about whether the stack was 8-byte aligned or not depending on the value of STKALIGN in the Configuration Control Register. This information is stored in bit 9 of the xPSR on the stack, and it is a 1 if the stack was forced to be 8-byte aligned.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uMemory formatslThe processor views memory as a linear collection of bytes numbered in ascending order from 0. For example:bytes 0-3 hold the first stored wordbytes 4-7 hold the second stored word.lThe processor can access data words in memory in little-endian format or big-endian format. It always accesses code in little-endian format.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uMemory formatsllittle-endian formatEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nCortex-M3的的编编程模式程模式uInstruction set summarylThis section provides:a summary of the processor 16-bit instructionsa summary of the processor 32-bit instructions.l略略Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nSystem ControluSummary of processor registerslDescribes the registers that control functionality. It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System debug registers;Debug interface port registers;Memory Protection Unit registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nSystem ControluSummary of processor registerslDescribes the registers that control functionality. It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System debug registers;Debug interface port registers;Memory Protection Unit registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.l主要介绍主要介绍NVICEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nNVICuNVIC register mapuThe NVIC space is split as follows:l0xE000E000-0xE000E00F:Interrupt Type Registerl0xE000E010-0xE000E0FF:System Timerl0xE000E100-0xE000ECFF:NVICl0xE000ED00-0xE000ED8F:System Control Block: CPUID System control, configuration, and status Fault reportingl0xE000EF00-0xE000EF0F:Software Trigger Exception Registerl0xE000EFD0-0xE000EFFF:ID space.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nNVICName of registerTypeAddressReset valueInterrupt Control Type RegisterRead-only0xE000E004 aAuxiliary Control RegisterRead/write0xE000E008 0x0SysTick Control and Status RegisterRead/write0xE000E010 0x00000000SysTick Reload Value RegisterRead/write0xE000E014 UnpredictableSysTick Current Value RegisterRead/write clear 0xE000E018 UnpredictableSysTick Calibration Value RegisterRead-only0xE000E01C STCALIBIrq 0 to 31 Set Enable RegisterRead/write0xE000E100 0x00000000. . . . . . . . .Irq 224 to 239 Set Enable RegisterRead/write0xE000E11C 0x00000000Irq 0 to 31 Clear Enable RegisterRead/write0xE000E180 0x00000000. . . . . . . . .Irq 224 to 239 Clear Enable RegisterRead/write0xE000E19C 0x00000000Irq 0 to 31 Set Pending RegisterRead/write0xE000E200 0x00000000. . . . . . . . .Irq 224 to 239 Set Pending RegisterRead/write0xE000E21C 0x00000000Irq 0 to 31 Clear Pending RegisterRead/write0xE000E280 0x00000000. . . . . . . . .Irq 224 to 239 Clear Pending Register Read/write0xE000E29C 0x00000000Irq 0 to 31 Active Bit RegisterRead-only0xE000E300 0x00000000. . . . . . . . .Irq 224 to 239 Active Bit RegisterRead-only0xE000E31C 0x00000000Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nNVICName of registerTypeAddressReset valueIrq 0 to 3 Priority RegisterRead/write0xE000E4000x00000000. . . . . . . . .Irq 236 to 239 Priority RegisterRead/write0xE000E4EC 0x00000000CPUID Base RegisterRead-only0xE000ED000x412FC230Interrupt Control State RegisterRead/write or read-only 0xE000ED040x00000000Vector Table Offset RegisterRead/write0xE000ED080x00000000Application Interrupt/Reset Control Register Read/write0xE000ED0C 0x00000000System Control RegisterRead/write0xE000ED100x00000000Configuration Control RegisterRead/write0xE000ED140x00000200System Handlers 4-7 Priority RegisterRead/write0xE000ED180x00000000System Handlers 8-11 Priority RegisterRead/write0xE000ED1C 0x00000000System Handlers 12-15 Priority RegisterRead/write0xE000ED200x00000000System Handler Control and State RegisterRead/write0xE000ED240x00000000Configurable Fault Status RegistersRead/write0xE000ED280x00000000Hard Fault Status RegisterRead/write0xE000ED2C 0x00000000Debug Fault Status RegisterRead/write0xE000ED300x00000000Mem Manage Address RegisterRead/write0xE000ED34UnpredictableBus Fault Address RegisterRead/write0xE000ED38UnpredictableAuxiliary Fault Status RegisterRead/write0xE000ED3C 0x00000000PFR0: Processor Feature register0Read-only0xE000ED400x00000030PFR1: Processor Feature register1Read-only0xE000ED440x00000200Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nNVICName of registerTypeAddressReset valueDFR0: Debug Feature register0Read-only0xE000ED480x00100000AFR0: Auxiliary Feature register0Read-only0xE000ED4C 0x00000000MMFR0: Memory Model Feature register0Read-only0xE000ED500x00000030MMFR1: Memory Model Feature register1Read-only0xE000ED540x00000000MMFR2: Memory Model Feature register2Read-only0xE000ED580x00000000MMFR3: Memory Model Feature register3Read-only0xE000ED5C 0x00000000ISAR0: ISA Feature register0Read-only0xE000ED600x01141110ISAR1: ISA Feature register1Read-only0xE000ED640x02111000ISAR2: ISA Feature register2Read-only0xE000ED680x21112231ISAR3: ISA Feature register3Read-only0xE000ED6C 0x01111110ISAR4: ISA Feature register4Read-only0xE000ED700x01310102Software Trigger Interrupt RegisterWrite Only0xE000EF00-Peripheral identification register (PID4)Read-only0xE000EFD0 0x04Peripheral identification register (PID5)Read-only0xE000EFD4 0x00Peripheral identification register (PID6)Read-only0xE000EFD8 0x00Peripheral identification register (PID7)Read-only0xE000EFDC 0x00Peripheral identification register Bits 7:0 (PID0)Read-only0xE000EFE0 0x00Peripheral identification register Bits 15:8 (PID1)Read-only0xE000EFE4 0xB0Peripheral identification register Bits 23:16 (PID2)Read-only0xE000EFE8 0x2BPeripheral identification register Bits 31:24 (PID3)Read-only0xE000EFEC 0x00Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nNVICName of registerTypeAddressReset valueComponent identification register Bits 7:0 (CID0)Read Only0xE000EFF00x0DComponent identification register Bits 15:8 (CID1)Read-only0xE000EFF40xE0Component identification register Bits 23:16 (CID2) Read-only0xE000EFF80x05Component identification register Bits 31:24 (CID3) Read-only0xE000EFFC 0xB1Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nMemory MapuDescribes the processor fixed memory map and its bit-banding feature. It contains the following sections:lAbout the memory maplBit-bandinglROM memory tableEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nMemory MapEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nMemory MapMemory MapInterfaceCodeInstruction fetches are performed over the ICode bus. Data accesses are performed over the DCode bus.SRAMInstruction fetches and data accesses are performed over the system bus.SRAM_bitband Alias region. Data accesses are aliases. Instruction accesses are not aliases.PeripheralInstruction fetches and data accesses are performed over the system bus.Periph_bitband Alias region. Data accesses are aliases. Instruction accesses are not aliases.External RAM Instruction fetches and data accesses are performed over the system bus.External Device Instruction fetches and data accesses are performed over the system bus.PrivatePeripheralBus(PPB)Accesses to:are performed to the processor internal PPB. Instrumentation Trace Macrocell (ITM) Nested Vectored Interrupt Controller (NVIC) Flashpatch and Breakpoint (FPB) Data Watchpoint and Trace (DWT) Memory Protection Unit (MPU)Accesses to:are performed over the external PPB interface. Trace Point Interface Unit (TPIU) Embedded Trace Macrocell (ETM) System areas of the PPB memory mapThis memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present, cannot change this.SystemSystem segment for vendor system peripherals. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nMemory MapuMemory region permissionslWBWA: Write back write allocateNameRegionDevice type XN CacheCode0x00000000-0x1FFFFFFFNormal-WTSRAM0x20000000-0x3FFFFFFFNormal-WBWA SRAM_1M+0000000- SRAM_31M+0100000- SRAM_bitband+2000000Internal- SRAM+4000000-Peripheral0x40000000-0x5FFFFFFFDeviceXN - Periph_1IM+0000000- Periph_31IM+0100000- Periph_bit band+2000000Internal- Peripheral+4000000-External RAM0x60000000-0x7FFFFFFFNormal-WBWAExternal RAM0x80000000-0x9FFFFFFFNormal-WTExternal Device0xA0000000-0xBFFFFFFFDeviceXN -External Device0xC0000000-0xDFFFFFFFDeviceXN -System0xE0000000-0xFFFFFFFF -XN -Private Peripheral Bus +0000000SO, sharedXN -Vendor_SYS+0100000DeviceXN -Notes:Private Peripheral Bus and System space at 0xE0000000 - 0xFFFFFFFF are permanentlyXN. The MPU cannot change this.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nMemory MapuBit-bandinglThe processor memory map includes two bit-band regions.These occupy the lowest 1MB of the SRAM and Peripheral memory regions respectively. These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory.lThe memory map has two 32-MB alias regions that map to two 1-MB bit-band regions:Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region.Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nBit-bandinguPrinciplelThe mapping formula is:One-bit Mapping to One-Word!bit_word_offset = (byte_offset32)+(bit_number4)bit_word_addr = bit_band_base+bit_word_offsetwhere:Bit_word_offset is the position of the target bit in the bit-band memory region.Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.Bit_number is the bit position (0-7) of the targeted bit.Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.Bit_band_base is the starting address of the alias region.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nBit-bandinguPrinciplelFigure shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:The alias word at 0x23FFFFE0 maps to bit 0 of the bit-band byte at 0x200FFFFF:0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + 0*4.The alias word at 0x23FFFFFC maps to bit 7 of the bit-band byte at 0x200FFFFF:0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + 7*4.The alias word at 0x22000000 maps to bit 0 of the bit-band byte at 0x20000000:0x22000000 = 0x22000000 + (0*32) + 0 *4.The alias word at 0x2200001C maps to bit 7 of the bit-band byte at 0x20000000:0x2200001C = 0x22000000 + (0*32) + 7*4.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nBit-bandinguFigureEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nBit-bandinguDirectly accessing an alias regionlWriting to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 cleared writes a 0 to the bit-band bit.Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nBit-bandinguDirectly accessing an alias regionlReading a word in the alias region returns either 0x01 or 0x00. A value of 0x01 indicates that the targeted bit in the bit-band region is set. A value of 0x00 indicates that the targeted bit is clear. Bits 31:1 are zero.uDirectly accessing a bit-band regionlYou can directly access the bit-band region with normal reads and writes, and writes to that region.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nROM memory tableOffsetValueNameDescription0x0000xFFF0F003NVICPoints to the NVIC at 0xE000E000.0x0040xFFF02002or 003 if presentDWTPoints to the Data Watchpoint and Trace block at 0xE0001000. Value has bit 0 set if DWT is present.0x0080xFFF03002or 003 if presentFPBPoints to the Flash Patch and Breakpoint block at 0xE0002000. Value has bit 0 set to 1 if FPB is present.0x00C0xFFF01002or 003 if presentITMPoints to the Instrumentation Trace block at 0xE0000000. Value has bit 0 set if ITM is present.0x0100xFFF41002or 003 if presentTPIUPoints to the TPIU. Value has bit 0 set to 1 if TPIU is present. TPIU is at 0xE0040000.0x0140xFFF42002or 003 if presentETMPoints to the ETM. Value has bit 0 set to 1 if ETM is present. ETM is at 0xE0041000.0x0180EndMarks the end of the ROM table. If CoreSight components are added, they are added starting from this location and the End marker is moved to the next location after the additional components.0xFCC0x1MEMTYPEBits 31:1 RAZ. Bit 0 is set when the system memory map is accessible using the DAP. Bit 0 is clear when only debug resources are accessible using the DAP.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nROM memory tableOffsetValueNameDescription0xFD00x0PID4-0xFD40x0PID5-0xFD80x0PID6-0xFDC0x0PID7-0xFE00x0PID0-0xFE40x0PID1-0xFE80x0PID2-0xFEC0x0PID3-0xFF00x0DCID0-0xFF40x10CID1-0xFF80x05CID2-0xFFC0xB1CID3-Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuDescribes the exception model of the processor. It containssections:lAbout the exception modellException typeslException prioritylPrivilege and stackslPre-emptionlTail-chaininglLate-arrivinglExitlResetslException control transferlSetting up multiple stackslAbort modellActivation levelslFlowchartsEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuAbout the exception modellNested Vectored Interrupt Controller = NVIClThe processor and NVIC prioritize and handle all exceptions. lAll exceptions are handled in Handler mode. lProcessor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). lThe vector is fetched in parallel to the state saving, enabling efficient interrupt entry. lThe processor supports tail-chaining that enables back-to-back interrupts without the overhead of state saving and restoration. Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuAbout the exception modellThe following features enable efficient, low latency exception handling:Automatic state saving and restoring. The processor pushes state registers on the stack before entering the ISR, and pops them after exiting the ISR with no instruction overhead.Automatic reading of the vector table entry that contains the ISR address in code memory or data SRAM. This is performed in parallel to the state saving.NoteVector table entries are ARM/Thumb interworking compatible. This causes bit 0 of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit 0 clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuAbout the exception modellThe following features enable efficient, low latency exception handling:Support for tail-chaining. In tail-chaining, the processor handles back-to-back interrupts without popping and pushing registers between ISRs.Dynamic reprioritization of interrupts.Closely-coupled interface between the processor core and the NVIC to enable early processing of interrupts and processing of late-arriving interrupts with higher priority.Configurable number of interrupts, from 1 to 240.Configurable number of interrupt priorities, from 3 to 8 bits (8 to 256 levels).Separate stacks and privilege levels for Handler and Thread modes.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuAbout the exception modellThe following features enable efficient, low latency exception handling:ISR control transfer using the calling conventions of the C/C+ standard ARM Architecture Procedure Call Standard (AAPCS).Priority masking to support critical regions.NoteThe number of interrupts, and bits of interrupt priority, are configured during implementation. Software can choose only to enable a subset of the configured number of interrupts, and can choose how many bits of the configured priorities to use.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException typeslVarious types of exceptions exist in the processor. lA fault is an exception that results from an error condition because of instruction execution. Faults can be reported synchronously or asynchronously to the instruction that caused them. lIn general, faults are reported synchronously. The Imprecise Bus Fault is an asynchronous fault supported in the ARMv7-M profile. A synchronous fault is always reported with the instruction that caused the fault. An asynchronous fault does not guarantee how it is reported with respect to the instruction that caused the fault.lFor more information on exceptions, see the ARMv7-M Architecture Reference Manual.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException typesExceptionType Position PriorityDescription-0-Stack top is loaded from first entry of vector table on reset.Reset13 (highest)Invoked on power up and warm reset. On first instruction, drops to lowest priority (Thread mode). This is asynchronous.NMI22Cannot be stopped or pre-empted by any exception but reset. This is asynchronous.Hard Fault31All classes of Fault, when the fault cannot activate because of priority or the Configurable Fault handler has been disabled. This is synchronous.MemoryManagement4Config-urableMemory Protection Unit (MPU) mismatch, including access violation and no match. This is synchronous. This is used even if the MPU is disabled or not present, to support the Executable Never (XN) regions of the default memory map.Bus Fault5Config-urablePre-fetch fault, memory access fault, and other address/memory related. This is synchronous when precise and asynchronous when imprecise.Usage Fault6Config-urableUsage fault, such as Undefined instruction executed or illegal state transition attempt. This is synchronous.-7-10-ReservedEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException typesExceptionType Position PriorityDescriptionSVCall11Config-urableSystem service call with SVC instruction. This is synchronous.DebugMonitor12Config-urableDebug monitor, when not halting. This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation.-13-ReservedPendSV14Config-urablePendable request for system service. This is asynchronous and only pended by software.SysTick15Config-urableSystem tick timer has fired. This is asynchronous.ExternalInterrupt16andmoreConfig-urableAsserted from outside the core, INTISR239:0, and fed through the NVIC (prioritized). These are all asynchronous.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException typeslTable shows the exception type, position, and priority. lPosition refers to the word offset from the start of the vector table. The lower numbers shown in the Priority column of the table are higher priority. lHow the types are activated, synchronously or asynchronously, is also shown. The exact meaning and use of priorities is explained in Exception priority.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException priority动作动作描述描述占先占先新的异常比当前的异常或线程的优先级更高并打断当前的流程，这是对挂起中断新的异常比当前的异常或线程的优先级更高并打断当前的流程，这是对挂起中断（pended interrupt）的响应。如果挂起中断的优先级比当前的）的响应。如果挂起中断的优先级比当前的ISR 或线程的优先或线程的优先级更高，则进入挂起中断的级更高，则进入挂起中断的ISR。如果一个。如果一个ISR 抢占了另一个抢占了另一个ISR，则产生了中断，则产生了中断嵌套。嵌套。在进入异常时，处理器自动保存其状态，将状态压栈。与此同时，取出相应的中在进入异常时，处理器自动保存其状态，将状态压栈。与此同时，取出相应的中断向量。当处理器状态被保存并且断向量。当处理器状态被保存并且ISR 的第一条指令进入处理器流水线的执行阶的第一条指令进入处理器流水线的执行阶段时，开始执行段时，开始执行ISR 的第一条指令。状态保存在系统总线上执行。取向量操作根的第一条指令。状态保存在系统总线上执行。取向量操作根据向量表所在位置可以在系统总线或据向量表所在位置可以在系统总线或DCode 总线上执行。见向量表偏移寄存器。总线上执行。见向量表偏移寄存器。末尾连锁末尾连锁(Tail-chain)末尾连锁（末尾连锁（Tail-chain ）是处理器用来加速中断响应的一种机制。在结束）是处理器用来加速中断响应的一种机制。在结束ISR 时，时，如果存在一个挂起中断，其优先级高于正在返回的如果存在一个挂起中断，其优先级高于正在返回的ISR 或线程，那么就会跳过出或线程，那么就会跳过出栈操作，转而将控制权让给新的栈操作，转而将控制权让给新的ISR。返回返回在没有挂起（在没有挂起（pending）异常或没有比被压栈的）异常或没有比被压栈的ISR 优先级更高的挂起异常时，处优先级更高的挂起异常时，处理器执行出栈操作，并返回到被压栈的理器执行出栈操作，并返回到被压栈的ISR 或线程模式。在响应或线程模式。在响应ISR 之后，处理之后，处理器通过出栈操作自动将处理器状态恢复为进入器通过出栈操作自动将处理器状态恢复为进入ISR 之前的状态。如果在状态恢复之前的状态。如果在状态恢复过程中出现一个新的中断，并且该中断的优先级比正在返回的过程中出现一个新的中断，并且该中断的优先级比正在返回的ISR 或线程更高，或线程更高， 则处理器放弃状态恢复操作并将新的中断作为则处理器放弃状态恢复操作并将新的中断作为tail-chain 来处理。来处理。迟来迟来Late-Late-arrivingarriving迟来是处理器用来加速占先的一种机制。如果在保存前一个占先的状态时出现一迟来是处理器用来加速占先的一种机制。如果在保存前一个占先的状态时出现一个优先级更高的中断，则处理器转去处理优先级更高的中断，开始该中断的取向个优先级更高的中断，则处理器转去处理优先级更高的中断，开始该中断的取向量操作。状态保存不会受到迟来的影响。因为被保存的状态对于两个中断都是一量操作。状态保存不会受到迟来的影响。因为被保存的状态对于两个中断都是一样的，状态保存继续执行不会被打断。处理器对迟来中断进行管理，直到样的，状态保存继续执行不会被打断。处理器对迟来中断进行管理，直到ISR 的的第一条指令进入处理器流水线的执行阶段。返回时，采用常规的第一条指令进入处理器流水线的执行阶段。返回时，采用常规的tail-chain 技术。技术。Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuException prioritylPriority levelsThe NVIC supports software-assigned priority levels. You can assign a priority level from 0 to 255 to an interrupt by writing to the eight-bit PRI_N field in an Interrupt Priority Register. Hardware priority decreases with increasing interrupt number. Priority level 0 is the highest priority level, and priority level 255 is the lowest. The priority level overrides the hardware priority.For example, if you assign priority level 1 to IRQ0 and priority level 0 to IRQ31, then IRQ31 has higher priority than IRQ0.NoteSoftware prioritization does not affect reset, Non-Maskable Interrupt (NMI), and hard fault. They always have higher priority than the external interrupts.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlThe following sections describe the behavior of the processor when it takes an exception:StackingLate-arrivingTail-chaining.lStackingWhen the processor invokes an exception, it automatically stores the following eight registers to the SP in the following order:Program Counter (PC)Processor Status Register (xPSR)r0-r3r12Link Register (LR).Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlStackingThe SP is decremented by eight words by the completion of the stack push. Figure shows the contents of the stack after an exception pre-empts the current program flow.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlStackingException entry stepsAction RestartableDescription Pusheight registersNo. Pushes xPSR, PC, r0, r1, r2, r3, r12, and LR on selected stack. Readvector tableYes. Late-arrivingexception cancause restart. Reads vector table from memory based on table base + (exception number 4). Read on the ICode bus can be done simultaneously with register pushes on the DCode bus. Read SP fromvector table No. On Reset only, updates SP to top of stack from vector table. Other exceptions do not modify SP except to select stack, push, and pop. Update PC No. Updates PC with vector table read location. Late-arriving exceptions cannot be processed until the first instruction starts to execute. Load pipeline Yes. Pre-emptionreloads pipeline fromnew vector table read. Loads instructions from location pointed to by vector table. This is done in parallel with register push. Update LR No. LR is set to EXC_RETURN to exit from exception. EXC_RETURN is one of 16 values as defined in ARMv7-M Architecture Reference Manual. Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlStackingEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlStackingThe NVIC indicates to the processor core, in the cycle after INTISR2 was received, that an interrupt has been received, and the processor initiates the stack push and vector fetch in the following cycle.When the stack push has completed, the first instruction of the ISR enters the execute stage of the pipeline. In the cycle that the ISR enters execute:ETMINSTAT2:0 indicates that the ISR has been entered (3b001). This is a 1-cycle pulse.CURRPRI7:0 indicates the priority of the active interrupt. CURRPRI remains asserted throughout the duration of the ISR. CURRPRI becomes valid when ETMINTSTAT indicates that the ISR has been entered (3b001).Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlStackingETMINTNUM8:0 indicates the number of the active interrupt. ETMINTNUM remains asserted throughout the duration of the ISR. ETMINTNUM becomes valid when ETMINTSTAT indicates that the ISR has been entered (3b001). Prior to that it indicates which ISR is being fetched.Figure shows that there is a 12-cycle latency from asserting the interrupt to the first instruction of the ISR executing.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlTail-chainingTail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions.Figure shows an example of tail-chaining. If a pending interrupt has higher priority than the highest-priority stacked exception, the stack push or pop is omitted, and the processor immediately fetches the vector for the pending interrupt. The ISR that is tail-chained into starts execution six cycles after exiting the previous ISR.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlTail-chainingEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlTail-chainingOn return from the last ISR, INTISR2 is of higher priority than any stacked ISR, or other pended interrupt, and so the processor tail-chains to the ISR corresponding to INTISR2. In the cycle that the ISR for INTISR2 enters execute:ETMINSTAT2:0 indicates that the ISR has been entered (3b001). This is a 1-cycle pulse.CURRPRI7:0 indicates the priority of the active interrupt. CURRPRI remains asserted throughout the duration of the ISR.ETMINTNUM8:0 indicates the number of the active interrupt. ETMINTNUM remains asserted throughout the duration of the ISR.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlLate-arrivingA late-arriving interrupt can pre-empt a previous interrupt if the first instruction of the previous ISR has not entered the Execute stage, and the late-arriving interrupt has a higher priority than the previous interrupt.A late-arriving interrupt causes a new vector address fetch and ISR prefetch. State saving is not performed for the late-arriving interrupt because it has already been performed for the initial interrupt and so does not have to be repeated.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlLate-arriving16+216+8Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlLate-arrivingIn Figure, INTISR8 pre-empts INTISR2. The state saving for INTISR2 is already done and is not required to be repeated. Figure shows the latest point at which INTISR8 can pre-empt before the first instruction of the ISR for INTISR2 enters Execute stage. A higher priority interrupt after that point is managed as a pre-emption.Figure shows the latest point at which INTISR9 can pre-empt before the first instruction of the ISR for INTISR8 enters Fetch stage. The ISR fetch for INTISR8 is aborted when INTISR9 is received, and the processor then initiates the vector fetch for INTISR9. A higher priority interrupt after that point is managed as pre-emption.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuPre-emptionlLate-arrivingIn the cycle that the ISR for INTISR9 enters execute:ETMINSTAT2:0 indicates that the ISR has been entered (3b001). This is a 1-cycle pulse.CURRPRI7:0 indicates the priority of the active interrupt. CURRPRI remains asserted throughout the duration of the ISR.ETMINTNUM8:0 indicates the number of the active interrupt. ETMINTNUM remains asserted throughout the duration of the ISR.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuExitlThe last instruction of an ISR loads the PC with value 0xFFFFFFFX that was LR on exception entry. This indicates to the processor that the ISR is complete, and the processor initiates the exception exit sequence. lException exitWhen returning from an exception, the processor is either:tail-chaining to a pending exception if the pending exception is of higher priority than all stacked exceptionsEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuExitlException exitreturning to the last stacked ISR if there are no pending exceptions or if the highest priority stacked exception is of higher priority than the highest priority pending exceptionreturning to the Thread mode if there are no pending or stacked exceptions.Table describes the postamble sequence.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuExitlException exitActionDescriptionPop eight registersPops PC, xPSR, r0, r1, r2, r3, r12 and LR from stack selected by EXC_RETURNand adjusts SP, if not pre-empted.Load current active interrupt numberLoads current active interrupt number from bits 8:0 of stacked IPSR word. Theand reverse stack-alignmentprocessor uses this to track which exception to return to and to clear theadjustmentactivation bit on return. When bits 8:0 are zero, the processor returns to ThreadMode.Select SPIf returning to an exception, SP is SP_main. If returning to Thread Mode, SP canbe SP_main or SP_process.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuExitlReturning the processor from an ISRException returns occur when one of the following instructions loads a value of 0xFFFFFFFX into the PC:POP/LDM which includes loading the PCLDR with PC as a destinationBX with any register.When used in this way, the value written to the PC is intercepted and is referred to as the EXC_RETURN value. EXC_RETURN3:0 provides return information as defined in Table.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuExitlReturning the processor from an ISREXC_RETURN3:0Description0bXXX0Reserved.0b0001Return to Handler mode. Exception return gets state from the main stack. On return execution uses the main stack.0b0011Reserved.0b01X1Reserved.0b1001Return to Thread mode. Exception return gets state from the main stack. On return execution uses the main stack.0b1101Return to Thread mode. Exception return gets state from the process stack. On return execution uses the process stack.0b1X11Reserved.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuResetslThe NVIC is reset at the same time as the core and controls the release of reset into the core. As a result, the behavior of reset is predictable. Table shows the reset behavior.Action Description NVIC resets, holds core in reset NVIC clears most of its registers. The processor is in Thread mode, priority is privileged, and the stack is set to Main. NVIC releases core from reset NVIC releases core from reset. Core sets stack Core reads the start SP, SP_main, from vector-table offset 0. Core sets PC and LR Core reads the start PC from vector-table offset 4. LR is set to 0xFFFFFFFF. Reset routine runs NVIC has interrupts disabled, and NMI and Hard Fault are not disabled. Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuResetslVector Table and ResetThe vector table at location 0 provides the vector table at reset. It must contain at least four values:stack top addressreset routine locationNMI ISR locationHard Fault ISR location.When interrupts are enabled, the vector table regardless of location, points to all mask-enabled exceptions. Also, the SVCall ISR location is populated if the SVC instruction is used.Embedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuResetslVector Table and ResetAn example of a full vector table:unsigned int stack_baseSTACK_SIZE;void ResetISR(void);void NmiISR(void);ISR_VECTOR_TABLE vector_table_at_0stack_base + sizeof(stack_base), /FD StackResetISR,NmiSR,FaultISR,0, / Populate if using MemManage (MPU)0, / Populate if using Bus fault0, / Populate if using Usage FaultEmbedded System Interface Design and Application信息信息学院学院Cortex-M3的总结的总结nExceptionsuResetslVector Table and ResetAn example of a full vector table:ISR_VECTOR_TABLE vector_table_at_00, 0, 0, 0, / reserved slotsSVCallISR,0, / Populate if using a debug monitor0, / Reserved0, / Populate if using pendable service request0, / Populate if using SysTick/ external interrupts start hereTimer1ISR,GpioInISRGpioOutISR,I2CIsr;Embedded System Interface Design and Application信息信息学院学院STM32F系列的特点系列的特点nSTM32系列系列产产品品编编号信息号信息u每每种种STM32的的产产品品都都由由16个个字字母母或或数数字字构构成成的的编编号号标标示示，用用户户向向ST订订货货时时必必须须使使用用这这个个编编号号指指定定需需要要的的产产品品。这这16个个字字符符分分为为8个个部部分分，下下面面通通过过一一个个例例子子说说明它们的意义：明它们的意义：uSTM32 F 103 C 6 T 7 xxxu 1 2 3 4 5 6 7 8l第第1部分：产品系列名，固定为部分：产品系列名，固定为STM32l第第2部分：产品类型；部分：产品类型；F 表示这是表示这是Flash产品产品l第第3部分：产品子系列；部分：产品子系列；101为基本型、为基本型、 103为增强型产品为增强型产品l第第4部分：管脚数目；部分：管脚数目；T = 36脚脚 C = 48脚脚 R = 64脚脚 V = 100脚脚 Z = 144脚脚Embedded System Interface Design and Application信息信息学院学院STM32F系列的特点系列的特点nSTM32系列系列产产品品编编号信息号信息uSTM32 F 103 C 6 T 7 xxxl第第5部分：闪存存储器容量：部分：闪存存储器容量：6=32KB，8=64KB，B=128KB，C=256KB，D=384K，E=512Kl第第6部分：封装信息：部分：封装信息：H = BGA，T = LQFP，U = VFQFPNl第第7部分：工作温度范围；部分：工作温度范围；l6=工业级，工业级，-40+85C，7=工业级，工业级，-40+105Cl第第8部部分分：可可选选项项；此此部部分分可可以以没没有有，可可以以用用于于标标示示内内部部固固件版本号。件版本号。l具体型号的更多信息需要参考具体型号的更多信息需要参考STM32数据手册数据手册.l下下表表是是所所有有ST6、ST7、ST10、STR7、STR9和和STM32系系列列产品的编号：产品的编号：Embedded System Interface Design and Application信息信息学院学院STM32F系列的特点系列的特点nSTM32系列系列产产品品编编号信息号信息uSTM32 F 103 C 6 T 7 xxxEmbedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103分分类类u主要类别主要类别lSTM32F103xClSTM32F103xDlSTM32F103xEu主要封装主要封装l如图所示如图所示u主要型号主要型号参参 考考 基本型号基本型号 STM32F103xC STM32F103RC、STM32F103VC、STM32F103ZC STM32F103xD STM32F103RD、STM32F103VD、STM32F103ZD STM32F103xE STM32F103RE、STM32F103ZE、STM32F103VE Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能u主要功能主要功能l内核内核ARM 32位的位的Cortex-M3 CPU最最 高高 72MHz工工 作作 频频 率率 ， 在在 存存 储储 器器 的的 0等等 待待 周周 期期 访访 问问 时时 可可 达达1.25DMips/MHz(Dhrystone 2.1)单周期乘法和硬件除法单周期乘法和硬件除法l存储器存储器从从256K至至512K字节的闪存程序存储器字节的闪存程序存储器高达高达64K字节的字节的SRAM带带4个个片片选选的的静静态态存存储储器器控控制制器器。支支持持CF卡卡、SRAM、PSRAM、NOR和和NAND存储器存储器并行并行LCD接口，兼容接口，兼容8080/6800模式模式Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能u时钟、复位和电源管理时钟、复位和电源管理l2.03.6伏供电和伏供电和I/O引脚引脚l上电上电/断电复位断电复位(POR/PDR)、可编程电压监测器、可编程电压监测器(PVD)l416MHz晶体振荡器晶体振荡器l内嵌经出厂调校的内嵌经出厂调校的8MHz的的RC振荡器振荡器l内嵌带校准的内嵌带校准的40kHz的的RC振荡器振荡器l带校准功能的带校准功能的32kHz RTC振荡器振荡器u低功耗低功耗l睡眠、停机和待机模式睡眠、停机和待机模式lVBAT为为RTC和后备寄存器供电和后备寄存器供电Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能u3个个12位位ADC，1s转换时间转换时间(多达多达21个输入通道个输入通道)l转换范围：转换范围：0至至3.6Vl三倍采样和保持功能三倍采样和保持功能l温度传感器温度传感器u2通道通道12位位D/A转换器转换器lDMA：12通道通道DMA控制器控制器l支支持持的的外外设设：定定时时器器、ADC、DAC、SDIO、I2S、SPI、I2C和和USARTu调试模式调试模式l串行单线调试串行单线调试(SWD)和和JTAG接口接口lCortex-M3内嵌跟踪模块内嵌跟踪模块(ETM)Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能u多达多达112个快速个快速I/O端口端口l51/80/112个个多多功功能能双双向向的的I/O口口，所所有有I/O口口可可以以映映像像到到16个外部中断；几乎所有端口均可容忍个外部中断；几乎所有端口均可容忍5V信号信号u多达多达11个定时器个定时器l多多达达4个个16位位定定时时器器，每每个个定定时时器器有有多多达达4个个用用于于输输入入捕捕获获/输出比较输出比较/PWM或脉冲计数的通道和增量编码器输入或脉冲计数的通道和增量编码器输入l2个个16位位带带死死区区控控制制和和紧紧急急刹刹车车，用用于于电电机机控控制制的的PWM高高级级控制定时器控制定时器l2个看门狗定时器个看门狗定时器(独立的和窗口型的独立的和窗口型的)l系统时间定时器：系统时间定时器：24位自减型计数器位自减型计数器l2个个16位基本定时器用于驱动位基本定时器用于驱动DACEmbedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能u多达多达13个通信接口个通信接口l多达多达2个个I2C接口接口(支持支持SMBus/PMBus)l多多达达5个个USART接接口口：支支持持ISO7816，LIN，IrDA接接口口和和调调制解调控制制解调控制l多达多达3个个SPI接口接口(18M位位/秒秒)，2个可复用为个可复用为I2S接口接口lCAN接口接口(2.0B 主动主动)lUSB 2.0全速接口全速接口lSDIO接口接口uCRC计算单元，计算单元，96位的芯片唯一代码位的芯片唯一代码u工作于工作于-40C至至+105C的温度范围的温度范围Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103功能功能uSTM32F103xx大大容容量量增增强强型型系系列列产产品品提提供供包包括括从从64脚至脚至144脚的脚的6种不同封装形式。种不同封装形式。u这这些些丰丰富富的的外外设设配配置置，使使得得STM32F103xx大大容容量量增增强型系列微控制器适合于多种应用场合：强型系列微控制器适合于多种应用场合：u电机驱动和应用控制电机驱动和应用控制u医疗和手持设备医疗和手持设备uPC游戏外设和游戏外设和GPS平台平台u工工业业应应用用：可可编编程程控控制制器器(PLC)、变变频频器器、打打印印机机和扫描仪和扫描仪u警报系统、视频对讲、和暖气通风空调系统等警报系统、视频对讲、和暖气通风空调系统等Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103xx比比较较u如表所示如表所示外设外设 STM32F103Rx STM32F103Vx STM32F103Zx 闪存闪存(K字节字节) 256 384 512 256 384 512 256 384512 SRAM(K字节字节) 48 64 48 64 48 64 FSMC(静态存储器控制器静态存储器控制器) 无无 有有有有 定时器定时器 通用通用 4个个(TIM2、TIM3、TIM4、TIM5) 高级控制高级控制 2个个(TIM1、TIM8) 基本基本 2个个(TIM6、TIM7) 通信通信 接口接口 SPI(I2S)3个个(SPI1、SPI2、SPI3)，其中，其中SPI2和和SPI3可作为可作为I2S通信通信 I2C 2个个(I2C1、I2C2) USART/UART 5个个(USART1、USART2、USART3、UART4、UART5) USB 1个个(USB 2.0全速全速) CAN 1个个(2.0B 主动主动) SDIO 1个个 GPIO端口端口 51 80 112 12位位ADC模块模块(通道数通道数) 3(16) 3(16) 3(21) 12位位DAC转换器转换器(通道数通道数) 2(2) CPU频率频率 72MHz 工作电压工作电压 2.03.6V 工作温度工作温度 环境温度：环境温度：-40+85/ /-40+105；结温度：；结温度：-40+125封装形式封装形式 LQFP64, ,WLCSP64 LQFP100, ,BGA100 LQFP144, ,BGA144 Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103xx比比较较u表中说明表中说明l对对于于LQFP100和和BGA100封封装装，只只有有FSMC的的Bank1和和Bank2可可以以使使用用。Bank1只只能能使使用用NE1片片选选支支持持多多路路复复用用NOR/PSRAM存存储储器器，Bank2只只能能使使用用NCE2片片选选支支持持一一个个16位位或或8位位的的NAND闪闪存存存存储储器器。因因为为没没有有端端口口G，不不能能使使用用FSMC的的中中断断功功能。能。lSPI2和和SPI3接接口口能能够够灵灵活活地地在在SPI模模式式和和I2S音音频频模模式式间间切切换。换。Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103xx比比较较u系列之间的全兼容性系列之间的全兼容性lSTM32F103xx是是一一个个完完整整的的系系列列，其其成成员员之之间间是是完完全全地地脚脚对脚兼容，软件和功能上也兼容。在参考手册中，对脚兼容，软件和功能上也兼容。在参考手册中，STM32F103x4和和STM32F103x6被归为小容量产品，被归为小容量产品，STM32F103x8和和STM32F103xB被归为中容量产品，被归为中容量产品，STM32F103xC、STM32F103xD和和STM32F103xE为大容量。为大容量。l小小容容量量和和大大容容量量产产品品是是中中等等容容量量产产品品的的延延伸伸，分分别别在在对对应应的的数据手册中介绍：数据手册中介绍：STM32F103x4/6和和STM32F103xC/D/E。小容量产品具有较小的闪存存储器、小容量产品具有较小的闪存存储器、RAM空间和较少的定时器和外设。空间和较少的定时器和外设。大大容容量量的的产产品品则则具具有有较较大大的的闪闪存存存存储储器器、RAM空空间间和和更更多多的的片片上上外外设设，如如SDIO、FSMC、I2S和和DAC等，同时保持与其它同系列的产品兼容。等，同时保持与其它同系列的产品兼容。STM32F103x4、STM32F103x6、 STM32F103xC、STM32F103xD和和STM32F103xE可可直直接接替替换换中中等等容容量量的的STM32F103x8/B产产品品，为为用用户户在在产品开发中尝试使用不同的存储容量提供了更大的自由度。产品开发中尝试使用不同的存储容量提供了更大的自由度。Embedded System Interface Design and Application信息信息学院学院STM32F103系列的特点系列的特点nSTM32F103xx比比较较uSTM32F103xx系列系列引脚引脚数目数目小容量产品小容量产品中等容量产品中等容量产品大容量产品大容量产品16K16K闪存闪存 32K闪存闪存 64K64K闪存闪存 128K128K闪存闪存256K256K闪存闪存384K384K闪存闪存512K512K闪存闪存6K RAM6K RAM10K RAM10K RAM20K RAM20K RAM20K RAM20K RAM48K48K或或64K(2) RAM64K(2) RAM64K RAM64K RAM64K RAM64K RAM1441443 3个个USART + 2USART + 2个个UARTUART4 4个个1616位定时器、位定时器、2 2个基本定时器个基本定时器3 3个个SPISPI、2 2个个I2SI2S、2 2个个I2CI2CUSBUSB、CANCAN、2 2个个PWMPWM定时器定时器3 3个个ADCADC、1 1个个DACDAC、1 1个个SDIOSDIOFSMC(100FSMC(100和和144144脚封装脚封装(3)(3)1001003 3个个USARTUSART3 3个个1616位定时器位定时器2 2个个SPISPI、2 2个个I2CI2CUSBUSB、CANCAN1 1个个PWMPWM定时器定时器1 1个个ADCADC64642 2个个USARTUSART2 2个个1616位定时器位定时器1 1个个SPISPI、1 1个个I2CI2CUSBUSB、CANCAN1 1个个PWMPWM定时器定时器2 2个个ADCADC48483636说明说明对于订购代码的温度尾缀对于订购代码的温度尾缀(6(6或或7)7)之后没有代码之后没有代码A A的产品，其对应的电气参数部分，请参的产品，其对应的电气参数部分，请参考考STM32F103x8/BSTM32F103x8/B中等容量产品数据手册。中等容量产品数据手册。只有只有CSPCSP封装的带封装的带256K256K闪存的产品，才具有闪存的产品，才具有64K64K的的RAMRAM。100100脚封装的产品中没有端口脚封装的产品中没有端口F F和端口和端口G G。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nCortex-M3核心并内嵌核心并内嵌FLAH和和SRAMlCortex-M3处处理理器器是是最最新新一一代代的的嵌嵌入入式式ARM处处理理器器，它它为为实实现现MCU的的需需要要提提供供了了低低成成本本的的平平台台、缩缩减减的的引引脚脚数数目目、降降低低的的系统功耗，同时提供卓越的计算性能和先进的中断系统响应。系统功耗，同时提供卓越的计算性能和先进的中断系统响应。lCortex-M3是是32位位的的RISC处处理理器器，提提供供额额外外的的代代码码效效率率，在通常在通常8和和16位系统的存储空间上发挥了位系统的存储空间上发挥了ARM内核的高性能。内核的高性能。lSTM32F103xC、STM32F103xD和和STM32F103xE增增强强系系列列拥有内置的拥有内置的ARM核心，因此它与所有的核心，因此它与所有的ARM工具和软件兼容。工具和软件兼容。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n内置内置FLASHu高达高达512KB内置内置Flash，用于存放程序和数据。，用于存放程序和数据。uSTM32的的CPU时时钟钟可可达达到到72MHz，但但是是由由于于半半导导体体制制造造工工艺艺的的限限制制，存存放放程程序序的的Flash存存储储器器不不可可能能达达到到这这么么高高的的工工作作频频率率，这这样样当当CPU直直接接访访问问Flash存存储储器器时必须插入等待周期以得到正确的结果。时必须插入等待周期以得到正确的结果。uSTM32的的内内部部Flash是是组组织织成成64位位宽宽度度，即即每每次次可可以以读读出出64位位；在在Flash与与CPU的的取取指指队队列列之之间间有有两两个个缓冲器，用于暂存缓冲器，用于暂存Flash中取出的指令。中取出的指令。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n内置内置SRAMu达达64K字字节节的的内内置置SRAM，CPU能能以以0等等待待周周期期访访问问(读读/写写)。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nCRC(循循环环冗余校冗余校验验)计计算算单单元元uCRC计计算算单单元元使使用用一一个个固固定定的的多多项项式式发发生生器器，从从一一个个32位的数据字产生一个位的数据字产生一个CRC码。码。u关于关于CRC算法算法l在在各各应应用用中中，基基于于CRC的的技技术术被被用用于于验验证证数数据据传传输输或或存存储储的的一一致致性性。在在EN/IEC 60335-1标标准准的的范范围围内内，它它提提供供了了一一种种检检测测闪闪存存存存储储器器错错误误的的手手段段，CRC计计算算单单元元可可以以用用于于实实时时地地计计算软件的签名，并与在链接和生成该软件时产生的签名对比。算软件的签名，并与在链接和生成该软件时产生的签名对比。lCRC算算法法最最重重要要的的参参数数当当然然是是生生成成多多项项式式，但但（余余数数）初初值值和和CRC数数据据最最高高位位的的位位置置也也是是很很重重要要的的两两个个参参数数，而而这这两两个个参参数数需需要要根根据据具具体体情情况况具具体体分分析析的的。初初值值一一般般是是全全0或或者者全全 1，CRC数据最高位一般在最低字节的最低位或者最高位。数据最高位一般在最低字节的最低位或者最高位。lCRC算算法法作作为为一一种种检检错错算算法法，它它的的着着眼眼点点是是出出错错概概率率高高地地方方的错误，这在一定程度上决定了后两个参数。的错误，这在一定程度上决定了后两个参数。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nFSMC(可配置的静可配置的静态态存存储储器控制器器控制器)uSTM32F103xC、STM32F103xD和和STM32F103xE增增强强型型系系列列集集成成了了FSMC模模块块。它它具具有有4个个片片选选输输出出，支支持持PC卡卡/CF卡、卡、SRAM、PSRAM、NOR和和NAND。u功能介绍：功能介绍：l三个三个FSMC中断源，经过逻辑或连到中断源，经过逻辑或连到NVIC单元；单元；l写入写入FIFO；l代码可以在除代码可以在除NAND闪存和闪存和PC卡外的片外存储器运行；卡外的片外存储器运行；l目目标标频频率率fCLK为为HCLK/2，即即当当系系统统时时钟钟为为72MHz时时，外外部部访访问问是是基基于于36MHz时时钟钟；系系统统时时钟钟为为48MHz时时，外外部部访访问问是是基基于于24MHz时钟。时钟。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nLCD并行接口并行接口uFSMC可可以以配配置置成成与与多多数数图图形形LCD控控制制器器的的无无缝缝连连接接，它它支支持持Intel 8080和和Motorola 6800的的模模式式，并并能能够够灵灵活活地地与与特特定定的的LCD接接口口。使使用用这这个个LCD并并行行接接口口可可以以很很方方便便地地构构建建简简易易的的图图形形应应用用环环境境，或或使使用用专专用用加加速控制器的高性能方案。速控制器的高性能方案。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n嵌套的向量式中断控制器嵌套的向量式中断控制器(NVIC)uSTM32F103x/D/E增增强强产产品品内内置置嵌嵌套套的的向向量量式式中中断断控控制制器器，能能够够处处理理多多达达60个个可可屏屏蔽蔽中中断断通通道道(不不包包括括16个个Cortex-M3的中断线的中断线)和和16个优先级。个优先级。l紧耦合的紧耦合的NVIC能够达到低延迟的中断响应处理能够达到低延迟的中断响应处理l中断向量入口地址直接进入内核中断向量入口地址直接进入内核l紧耦合的紧耦合的NVIC接口接口l允许中断的早期处理允许中断的早期处理l处理晚到的较高优先级中断处理晚到的较高优先级中断l支持中断尾部链接功能支持中断尾部链接功能l自动保存处理器状态自动保存处理器状态l中断返回时自动恢复，无需额外指令开销中断返回时自动恢复，无需额外指令开销l该模块以最小的中断延迟提供灵活的中断管理功能。该模块以最小的中断延迟提供灵活的中断管理功能。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n外部中断外部中断/事件控制器事件控制器(EXTI)u外外部部中中断断/事事件件控控制制器器包包含含19个个边边沿沿检检测测器器，用用于于产产生中断生中断/事件请求。事件请求。u每每个个中中断断线线都都可可以以独独立立地地配配置置它它的的触触发发事事件件(上上升升沿沿或下降沿或双边沿或下降沿或双边沿)，并能够单独地被屏蔽；，并能够单独地被屏蔽；u有一个挂起寄存器维持所有中断请求的状态。有一个挂起寄存器维持所有中断请求的状态。uEXTI可以检测到脉冲宽度小于内部可以检测到脉冲宽度小于内部APB2的时钟周期。的时钟周期。u多达多达112个通用个通用I/O口连接到口连接到16个外部中断线。个外部中断线。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n时钟时钟和启和启动动u系系统统时时钟钟的的选选择择是是在在启启动动时时进进行行，复复位位时时内内部部8MHz的的RC振振荡荡器器被被选选为为默默认认的的CPU时时钟钟，随随后后可可以以选选择择外外部的、具失效监控的部的、具失效监控的416MHz时钟；时钟；u当当检检测测到到外外部部时时钟钟失失效效时时，它它将将被被隔隔离离，系系统统将将自自动动地地切切换换到到内内部部的的RC振振荡荡器器，如如果果使使能能了了中中断断，软软件件可可以以接接收收到到相相应应的的中中断断。同同样样，在在需需要要时时可可以以采采取取对对PLL时钟完全的中断管理。时钟完全的中断管理。u多多 个个 预预 分分 频频 器器 用用 于于 配配 置置 AHB的的 频频 率率 、 高高 速速APB(APB2)和低速和低速APB(APB1)区域。区域。uAHB和和高高速速APB的的最最高高频频率率是是72MHz，低低速速APB的的最最高频率为高频率为36MHz。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n自自举举模式模式uSTM32的的芯芯片片上上都都有有两两个个管管脚脚BOOT0和和BOOT1，在在芯芯片片复复位位时时其其电电平平状状态态决决定定了了芯芯片片复复位位后后开开始始执执行行程程序区域：序区域：lBOOT1=x, BOOT0=0：从从用用户户闪闪存存启启动动，这这是是正正常常的的工工作作模式。模式。lBOOT1=0, BOOT0=1：从从系系统统存存储储器器启启动动，这这种种模模式式启启动动的程序功能由厂家设置。的程序功能由厂家设置。lBOOT1=1, BOOT0=1：从从内内置置SRAM启启动动，这这种种模模式式可可以以用用于调试。于调试。l自自举举加加载载程程序序(Bootloader)存存放放于于系系统统存存储储器器中中，可可以以通通过过USART1对闪存重新编程。对闪存重新编程。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n自自举举模式模式uSTM32三三种种启启动动模模式式对对应应的的存存储储介介质质均均是是芯芯片片内内置置的，是：的，是：l1）用户闪存）用户闪存 = 芯片内置的芯片内置的Flash。l2）SRAM = 芯片内置的芯片内置的RAM区，就是内存。区，就是内存。l3）系系统统存存储储器器 = 芯芯片片内内部部一一块块特特定定的的区区域域，芯芯片片出出厂厂时时在在这这个个区区域域预预置置了了一一段段Bootloader，就就是是通通常常说说的的ISP程程序序。这这个个区区域域的的内内容容在在芯芯片片出出厂厂后后没没有有人人能能够够修修改改或或擦擦除除，即即它它是是一个一个ROM区。区。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n供供电电方案方案uVDD=2.03.6V：VDD引引脚脚为为I/O引引脚脚和和内内部部调调压压器供电。器供电。uVSSA，VDDA=2.03.6V：为为ADC、复复位位模模块块、RC振振荡荡器器和和PLL的的模模拟拟部部分分提提供供供供电电。使使用用ADC时时，VDDA不不得得小小于于2.4V。VDDA和和VSSA必必须须分分别别连连接接到到VDD和和VSS。uVBAT=1.83.6V：当当关关闭闭VDD时时，（通通过过内内部部电电源源切切换换器器）为为RTC、外外部部32kHz振振荡荡器器和和后后备备寄寄存存器器供供电。电。u关于如何连接电源引脚的详细信息，参见供电方案。关于如何连接电源引脚的详细信息，参见供电方案。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n供供电监电监控器控器u内内部部集集成成了了上上电电复复位位(POR)/掉掉电电复复位位(PDR)电电路路，该该电电路路始始终终处处于于工工作作状状态态，保保证证系系统统在在供供电电超超过过2V时时工工作作；当当VDD低低于于设设定定的的阈阈值值(VPOR/PDR)时时，置置器器件件于复位状态，而不必使用外部复位电路。于复位状态，而不必使用外部复位电路。u内内置置一一个个可可编编程程电电压压监监测测器器(PVD)，监监视视VDD/VDDA供供电电并并与与阈阈值值VPVD比比较较，当当VDD低低于于或或高高于于阀阀值值VPVD时时产产生生中中断断，中中断断处处理理程程序序可可以以发发出出警警告告信信息息或或将将微微控制器转入安全模式。控制器转入安全模式。PVD功能需要通过程序开启。功能需要通过程序开启。u如何使用如何使用STM32的的PVD对电源的电压进行监控。对电源的电压进行监控。u用用户户在在使使用用STM32时时，可可以以利利用用其其内内部部的的PVD对对VDD的的电电压压进进行行监监控控，通通过过电电源源控控制制寄寄存存器器(PWR_CR)中中的的PLS2:0位来设定监控的电压值。位来设定监控的电压值。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n电压调压电压调压器器u调调压压器器有有三三个个操操作作模模式式：主主模模式式(MR)、低低功功耗耗模模式式(LPR)和关断模式。和关断模式。l主模式主模式(MR)用于正常的运行操作用于正常的运行操作l低功耗模式低功耗模式(LPR)用于用于CPU的停机模式的停机模式l关关断断模模式式用用于于CPU的的待待机机模模式式：调调压压器器的的输输出出为为高高阻阻状状态态，内内核核电电路路的的供供电电切切断断，调调压压器器处处于于零零消消耗耗状状态态(但但寄寄存存器器和和SRAM的内容将丢失的内容将丢失)u调调压压器器在在复复位位后后始始终终处处于于工工作作状状态态，在在待待机机模模式式下下关闭处于高阻输出。关闭处于高阻输出。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n低功耗模式低功耗模式uSTM32F103xC/D/E支支持持三三种种低低功功耗耗模模式式，可可在在要要求求低低功功耗耗、短短启启动动时时间间和和多多种种唤唤醒醒事事件件之之间间达达到到最最佳佳的平衡。的平衡。u三种低功耗模式三种低功耗模式l睡睡眠眠模模式式：在在睡睡眠眠模模式式，只只有有CPU停停止止，所所有有外外设设处处于于工工作作状态并可在发生中断状态并可在发生中断/事件时唤醒事件时唤醒CPU。l停停机机模模式式：在在保保持持SRAM和和寄寄存存器器内内容容不不丢丢失失的的情情况况下下，停停机机模模式式可可以以达达到到最最低低的的电电能能消消耗耗。在在停停机机模模式式下下，停停止止所所有有内内部部1.8V部部分分的的供供电电，PLL、HSI的的RC振振荡荡器器和和HSE晶晶体体振振荡荡器器被被关关闭闭，调调压压器器可可以以被被置置于于普普通通模模式式或或低低功功耗耗模模式式。可可以以通通过过任任一一配配置置成成EXTI的的信信号号把把微微控控制制器器从从停停机机模模式式中中唤唤醒醒，EXTI信信号号可可以以是是16个个外外部部I/O口口之之一一、PVD的的输输出出、RTC闹闹钟钟或或USB的唤醒信号。的唤醒信号。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n低功耗模式低功耗模式u三种低功耗模式三种低功耗模式l待待机机模模式式：达达到到最最低低的的电电能能消消耗耗。其其内内部部的的电电压压调调压压器器被被关关闭闭，因因此此所所有有内内部部1.8V部部分分的的供供电电被被切切断断；PLL、HSI的的RC振振荡荡器器和和HSE晶晶体体振振荡荡器器也也被被关关闭闭；待待机机后后，SRAM和和寄寄存存器器的的内内容容将将消消失失，但但后后备备寄寄存存器器的的内内容容不不变变，待待机机电电路路仍仍工工作作。从从待待机机模模式式退退出出的的条条件件是是：NRST上上的的外外部部复复位位信信号号、IWDG复复位位、WKUP引脚上的一个上升边沿或引脚上的一个上升边沿或RTC的闹钟到时。的闹钟到时。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nDMAu灵灵活活的的12路路通通用用DMA(DMA1上上有有7个个通通道道，DMA2上上有有5个通道个通道)可以管理：可以管理：l存储器到存储器；存储器到存储器；l设备到存储器；设备到存储器；l存储器到设备的数据传输；存储器到设备的数据传输；l2个个DMA控控制制器器支支持持环环形形缓缓冲冲区区的的管管理理，避避免免了了控控制制器器传传输输到到达缓冲区结尾时所产生的中断。达缓冲区结尾时所产生的中断。l每每个个通通道道都都有有专专门门的的硬硬件件DMA请请求求逻逻辑辑，同同时时可可以以由由软软件件触触发发每每个个通通道道；传传输输的的长长度度、传传输输的的源源地地址址和和目目标标地地址址都都可可以以通通过软件单独设置。过软件单独设置。uDMA可以用于主要的外设可以用于主要的外设lSPI、I2C、USART，通通用用、基基本本和和高高级级控控制制定定时时器器TIMx，DAC、I2S、SDIO和和ADC。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nRTC（实时时钟实时时钟）和）和BKR（后（后备备寄存器）寄存器）uRTC和和BKR通通过过一一个个开开关关供供电电，在在VDD有有效效时时该该开开关关选择选择VDD供电，否则由供电，否则由VBAT引脚供电。引脚供电。lBKR(42个个16位位的的寄寄存存器器)可可以以用用于于在在关关闭闭VDD时时，保保存存84个个字字节节的的用用户户应应用用数数据据。RTC和和BKR不不会会被被系系统统或或电电源源复复位位源源复复位；当从待机模式唤醒时，也不会被复位。位；当从待机模式唤醒时，也不会被复位。lRTC具具有有一一组组连连续续运运行行的的计计数数器器，可可以以提提供供日日历历时时钟钟功功能能，还还具具有有闹闹钟钟中中断断和和阶阶段段性性中中断断功功能能。RTC的的时时钟钟可可以以使使用用外外部部32.768kHz的的振振荡荡器器、内内部部RC振振荡荡器器或或高高速速的的外外部部时时钟钟的的128分分频频。内内部部RC的的典典型型频频率率为为40kHz，为为补补偿偿晶晶体体的的偏偏差差，可可以以通通过过输输出出一一个个512Hz的的信信号号对对RTC的的时时钟钟进进行行校校准准。RTC具具有有一一个个32位位的的可可编编程程计计数数器器，使使用用比比较较寄寄存存器器可可以以进进行行长长时时间间的的测测量量。有有一一个个20位位的的预预分分频频器器用用于于时时基基时时钟钟，默默认认情情况况下下时钟为时钟为32.768kHz时，它将产生一个时，它将产生一个1秒长的时间基准。秒长的时间基准。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗uSTM32F103xx包包含含最最多多2个个高高级级控控制制定定时时器器、4个个普普通通定定时时器器和和2个个基基本本定定时时器器，以以及及2个个看看门门狗狗定定时时器器和和1个系统嘀嗒定时器。个系统嘀嗒定时器。u高级控制定时器、普通定时器和基本定时器比较：高级控制定时器、普通定时器和基本定时器比较：定时器定时器 计数器计数器分辩率分辩率 计数器计数器类型类型 预分频预分频系数系数 产生产生DMA请求请求捕获捕获/比较比较通道通道 互补互补输出输出TIM1 TIM8 16位位 向上向上/ /向下向下向上向上/下下 165536之间之间的任意整数的任意整数 可以可以 4 有有 TIM2 TIM3 TIM4 TIM5 16位位 向上向上/ /向下向下向上向上/下下 165536之间之间的任意整数的任意整数 可以可以 4 没有没有 TIM6 TIM7 16位位 向上向上 165536之间之间的任意整数的任意整数 可以可以 0 没有没有 Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗u高级控制定时器高级控制定时器l主要包括主要包括TIM1和和TIM8；lTIM1和和TIM8可可以以看看成成是是分分配配到到6个个通通道道的的三三相相PWM发发生生器器，具有带死区插入的互补具有带死区插入的互补PWM输出。四个独立的通道可以用于：输出。四个独立的通道可以用于：输入捕获输入捕获输出比较输出比较产生产生PWM(边缘或中心对齐模式边缘或中心对齐模式)单脉冲输出单脉冲输出l配配置置为为16位位标标准准定定时时器器时时，它它与与TIMx定定时时器器具具有有相相同同的的功功能。配置为能。配置为16位位PWM发生器时，具有全调制能力发生器时，具有全调制能力(0100%)。l在在调调试试模模式式下下，计计数数器器可可以以被被冻冻结结，同同时时PWM输输出出被被禁禁止止，从而切断由这些输出所控制的开关。从而切断由这些输出所控制的开关。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗u高级控制定时器高级控制定时器l很很多多功功能能都都与与标标准准的的TIM定定时时器器相相同同，内内部部结结构构也也相相同同，因因此此高高级级控控制制定定时时器器可可以以通通过过定定时时器器链链接接功功能能与与TIM定定时时器器协协同同操作，提供同步或事件链接功能。操作，提供同步或事件链接功能。u通用定时器通用定时器(TIMx)l主要包括主要包括TIMx；lSTM32F103xx增增强强型型系系列列产产品品中中，内内置置了了多多达达4个个可可同同步步运运行行的的标标准准定定时时器器(TIM2、TIM3、TIM4和和TIM5)。每每个个定定时时器器都都有有一一个个16位位的的自自动动加加载载递递加加/递递减减计计数数器器、一一个个16位位的的预预分分频频器器和和4个个独独立立的的通通道道，每每个个通通道道都都可可用用于于输输入入捕捕获获、输输出出比比较较、PWM和和单单脉脉冲冲模模式式输输出出，在在最最大大的的封封装装配配置置中中可可提提供供最最多多16个输入捕获、输出比较或个输入捕获、输出比较或PWM通道。通道。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗u通用定时器通用定时器(TIMx)l还还能能通通过过定定时时器器链链接接功功能能与与高高级级控控制制定定时时器器共共同同工工作作，提提供供同同步步或或事事件件链链接接功功能能。在在调调试试模模式式下下，计计数数器器可可以以被被冻冻结结。任任一一标标准准定定时时器器都都能能用用于于产产生生PWM输输出出。每每个个定定时时器器都都有有独独立立的的DMA请求机制。请求机制。l这这些些定定时时器器还还能能够够处处理理增增量量编编码码器器的的信信号号，也也能能处处理理1至至3个个霍尔传感器的数字输出。霍尔传感器的数字输出。u基本定时器基本定时器l主要包括主要包括TIM6和和TIM7；l这这2个个定定时时器器主主要要是是用用于于产产生生DAC触触发发信信号号，也也可可当当成成通通用用的的16位时基计数器。位时基计数器。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗u独立看门狗独立看门狗l独独立立的的看看门门狗狗是是基基于于一一个个12位位的的递递减减计计数数器器和和一一个个8位位的的预预分分频频器器，它它由由一一个个内内部部独独立立的的40kHz的的RC振振荡荡器器提提供供时时钟钟；因因为为这这个个RC振振荡荡器器独独立立于于主主时时钟钟，所所以以它它可可运运行行于于停停机机和和待待机机模模式式。它它可可以以被被当当成成看看门门狗狗用用于于在在发发生生问问题题时时复复位位整整个个系系统统，或或作作为为一一个个自自由由定定时时器器为为应应用用程程序序提提供供超超时时管管理理。通通过过选选项项字字节节可可以以配配置置成成是是软软件件或或硬硬件件启启动动看看门门狗狗。在在调调试试模模式式下下，计计数数器器可以被冻结。可以被冻结。u窗口看门狗窗口看门狗l窗窗口口看看门门狗狗内内有有一一个个7位位的的递递减减计计数数器器，并并可可以以设设置置成成自自由由运运行行。它它可可以以被被当当成成看看门门狗狗用用于于在在发发生生问问题题时时复复位位整整个个系系统统。它它由由主主时时钟钟驱驱动动，具具有有早早期期预预警警中中断断功功能能；在在调调试试模模式式下下，计计数器可以被冻结。数器可以被冻结。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n定定时时器和看器和看门门狗狗u系统时基定时器系统时基定时器l这这个个定定时时器器是是专专用用于于实实时时操操作作系系统统，也也可可当当成成一一个个标标准准递递减减计数器。它具有下述特性：计数器。它具有下述特性：24位的递减计数器位的递减计数器自动重加载功能自动重加载功能当计数器为当计数器为0时能产生一个可屏蔽系统中断时能产生一个可屏蔽系统中断可编程时钟源可编程时钟源Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nI2C总线总线u多多达达2个个I2C总总线线接接口口，能能够够工工作作于于多多主主模模式式或或从从模模式，支持标准和快速模式。式，支持标准和快速模式。uI2C接接口口支支持持7位位或或10位位寻寻址址，7位位从从模模式式时时支支持持双双从地址寻址。内置了硬件从地址寻址。内置了硬件CRC发生器发生器/校验器。校验器。u可可以以使使用用DMA操操作作并并支支持持SMBus总总线线2.0版版/PMBus总线。总线。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n通用同步通用同步/异步收异步收发发器器(USART)uSTM32F103xx内内置置了了3个个通通用用同同步步/异异步步收收发发器器(USART1、USART2和和USART3)，和和2个个通通用用异异步步收收发发器器(UART4和和UART5)。u这这5个个接接口口提提供供异异步步通通信信、支支持持IrDA/SIR/ENDEC传传输输编编解解码码、多多处处理理器器通通信信模模式式、单单线线半半双双工工通通信信模模式和式和LIN主主/从。从。uUSART1接接口口通通信信速速率率可可达达4.5兆兆位位/秒秒，其其他他接接口口的通信速率可达的通信速率可达2.25兆位兆位/秒。秒。uUSART1、USART2和和USART3接接口口具具有有硬硬件件的的CTS和和RTS信信号号管管理理、兼兼容容ISO7816的的智智能能卡卡模模式式和和类类SPI通通信信模模式式，除除了了UART5之之外外所所有有其其他他接接口口都都可可以以使使用用DMA操作。操作。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n串行外串行外设设接口接口(SPI)u包包括括3个个SPI接接口口。在在从从或或主主模模式式下下，全全双双工工和和半半双双工工的的通通信信速速率率可可达达18兆兆位位/秒秒。3位位的的预预分分频频器器可可产产生生8种种主主模模式式频频率率，可可配配置置成成每每帧帧8位位或或16位位。硬硬件件的的CRC产生产生/校验支持基本的校验支持基本的SD卡和卡和MMC模式。模式。u所有的所有的SPI接口都可以使用接口都可以使用DMA操作。操作。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nI2S(芯片互芯片互联联音音频频)接口接口u包包括括2个个标标准准的的I2S接接口口(与与SPI2和和SPI3复复用用)。可可以以工工作作于于主主或或从从模模式式，这这2个个接接口口可可以以配配置置为为16位位或或32位位传传输输，亦亦可可配配置置为为输输入入或或输输出出通通道道，支支持持音音频频采采样频率从样频率从8kHz到到48kHz。u当当任任一一个个或或两两个个I2S接接口口配配置置为为主主模模式式，它它的的主主时时钟钟可可以以以以256倍倍采采样样频频率率输输出出给给外外部部的的DAC或或CODEC(解解码器码器)。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nSDIOuSD/SDIO/MMC主主机机接接口口可可以以支支持持MMC卡卡系系统统规规范范4.2版版中中的的3个个不不同同的的数数据据总总线线模模式式：1位位(默默认认)、4位位和和8位位。在在8位位模模式式下下，该该接接口口可可以以使使数数据据传传输输速速率率达达到到48MHz，该接口兼容，该接口兼容SD存储卡规范存储卡规范2.0版。版。uSDIO存存储储卡卡规规范范2.0版版支支持持两两种种数数据据总总线线模模式式：1位位(默认默认)和和4位。位。u目目前前的的芯芯片片版版本本只只能能一一次次支支持持一一个个SD/SDIO/MMC 4.2版版的的卡卡，但但可可以以同同时时支支持持多多个个MMC 4.1版版或或之之前前版本的卡。版本的卡。u除除了了SD/SDIO/MMC，这这个个接接口口完完全全与与CE-ATA数数字字协议版本协议版本1.1兼容。兼容。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n控制器区域网控制器区域网络络(CAN)uCAN接接口口兼兼容容规规范范2.0A和和2.0B(主主动动)，位位速速率率高高达达1兆兆位位/秒秒。它它可可以以接接收收和和发发送送11位位标标识识符符的的标标准准帧帧，也也可可以以接接收收和和发发送送29位位标标识识符符的的扩扩展展帧帧。具具有有3个个发发送送邮箱和邮箱和2个接收个接收FIFO，3级级14个可调节的滤波器。个可调节的滤波器。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n通用串行通用串行总线总线(USB)uSTM32F103xC、STM32F103xD和和STM32F103xE增增强强型型系系列列产产品品，内内嵌嵌一一个个兼兼容容全全速速USB的的设设备备控控制制器器，遵遵循循全全速速USB设设备备(12兆兆位位/秒秒)标标准准，端端点点可可由由软软件件配配置置，具具有有待待机机/唤唤醒醒功功能能。USB专专用用的的48MHz时时钟钟由由内内部部主主PLL直直接接产产生生(时时钟钟源源必必须须是是一一个个HSE晶晶体体振振荡荡器器)。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n通用通用输输入入输输出接口出接口(GPIO)u每每个个GPIO引引脚脚都都可可以以由由软软件件配配置置成成输输出出(推推挽挽或或开开漏漏)、输输入入(带带或或不不带带上上拉拉或或下下拉拉)或或复复用用的的外外设设功功能能端端口口。多多数数GPIO引引脚脚都都与与数数字字或或模模拟拟的的复复用用外外设设共共用用。除除了了具具有有模模拟拟输输入入功功能能的的端端口口，所所有有的的GPIO引引脚脚都都有有大电流通过能力。大电流通过能力。u在在需需要要的的情情况况下下，I/O引引脚脚的的外外设设功功能能可可以以通通过过一一个个特定的操作锁定，以避免意外的写入特定的操作锁定，以避免意外的写入I/O寄存器。寄存器。u在在APB2上的上的I/O脚可达脚可达18MHz的翻转速度。的翻转速度。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n通用通用输输入入输输出接口出接口(GPIO)u共有共有8种模式，可以通过编程选择：种模式，可以通过编程选择：l 1. 浮空输入浮空输入l 2. 带上拉输入带上拉输入l 3. 带下拉输入带下拉输入l 4. 模拟输入模拟输入l 5. 开漏输出开漏输出(此模式可实现此模式可实现hotpower说的真双向说的真双向IO)l 6. 推挽输出推挽输出l 7. 复用功能的推挽输出复用功能的推挽输出l 8. 复用功能的开漏输出复用功能的开漏输出l模式模式7和模式和模式8需根据具体的复用功能决定。需根据具体的复用功能决定。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nADC(模模拟拟/数字数字转换转换器器)uSTM32F103xx内内嵌嵌3个个12位位的的ADC，每每个个ADC共共用用多多达达21个个外外部部通通道道，可可实实现现单单次次或或扫扫描描转转换换。在在扫扫描描模式下，自动进行在选定的一组模拟输入上的转换。模式下，自动进行在选定的一组模拟输入上的转换。uADC接口上的其它逻辑功能包括：接口上的其它逻辑功能包括：l同步的采样和保持同步的采样和保持l交叉的采样和保持交叉的采样和保持l单次采样单次采样uADC可以使用可以使用DMA操作。操作。u模模拟拟看看门门狗狗功功能能允允许许精精准准地地监监视视一一路路、多多路路或或所所有有选选中中的的通通道道，当当被被监监视视的的信信号号超超出出预预置置的的阈阈值值时时，将将产生中断。产生中断。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nADC(模模拟拟/数字数字转换转换器器)u由由标标准准定定时时器器(TIMx)和和高高级级控控制制定定时时器器(TIM1和和TIM8)产产生生的的事事件件，可可以以分分别别内内部部级级联联到到ADC的的开开始始触触发和注入触发，应用程序能使发和注入触发，应用程序能使AD转换与时钟同步。转换与时钟同步。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述nDAC(数字数字/模模拟拟信号信号转换转换器器)u两两个个12位位带带缓缓冲冲的的DAC通通道道可可以以用用于于转转换换2路路数数字字信信号号成成为为2路路模模拟拟电电压压信信号号并并输输出出。这这项项功功能能内内部部是是通通过过集成的电阻串和反向的放大器实现。集成的电阻串和反向的放大器实现。u这个双数字接口支持下述功能：这个双数字接口支持下述功能：l两个两个DAC转换器：各有一个输出通道转换器：各有一个输出通道l8位或位或12位单调输出位单调输出12位模式下的左右数据对齐位模式下的左右数据对齐l同步更新功能同步更新功能产生噪声波产生噪声波l产生三角波产生三角波双双DAC通道独立或同步转换通道独立或同步转换l每个通道都可使用每个通道都可使用DMA功能功能外部触发进行转换外部触发进行转换l输入参考电压输入参考电压 VREF+lSTM32F103x有有8个个触触发发DAC转转换换的的输输入入。DAC通通道道可可以以由由定定时器的更新输出触发，更新输出也可连接到不同的时器的更新输出触发，更新输出也可连接到不同的DMA通道。通道。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n温度温度传传感器感器uSTM32内置一个温度传感器，其功能为内置一个温度传感器，其功能为l产生产生1个随温度线性变化的电压，电压范围个随温度线性变化的电压，电压范围2VVDDA3.6V。l温温度度传传感感器器在在内内部部被被连连接接到到ADC1_IN16的的输输入入通通道道上上，用用于于将传感器的输出转换到数字数值。将传感器的输出转换到数字数值。uSTM32温度传感器的使用和计算温度传感器的使用和计算l通过通过ADC_IN16读出电压，计算公式：读出电压，计算公式：Temperature(in) = (V25- VSENSE) / Avg_Slope + 25Vsense是是在在ADC_IN16读读到到的的数数值值。Avg_Slope就就是是温温度度与与ADC数数值值转转换的斜率。换的斜率。V25 最小最小=1.34V 典型典型=1.43V 最大最大=1.52VAvg_Slope 最小最小=4.0 典型典型=4.3 最大最大=4.6 单位是单位是 mV/在在XY坐坐标标系系中中，X轴轴为为ADC的的电电压压，Y轴轴为为温温度度；如如果果X轴轴电电压压为为V25时时，Y轴轴即即为为25；当当读读出出的的电电压压是是其其它它数数值值时时，即即读读出出的的电电压压是是Vsense时时，使用这个公式就可以得到温度的数值。使用这个公式就可以得到温度的数值。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n串行串行单线单线JTAG调试调试口口(SWJ-DP)u内内嵌嵌ARM的的SWJ-DP接接口口，是是一一个个结结合合了了JTAG和和串串行行单单线线调调试试的的接接口口，可可以以实实现现串串行行单单线线调调试试接接口口或或JTAG接口的连接。接口的连接。uJTAG的的TMS和和TCK信信号号分分别别与与SWDIO和和SWCLK共共用用，TMS脚脚上上的的一一个个特特殊殊的的信信号号序序列列用用于于在在JTAG-DP和和SW-DP间切换。间切换。Embedded System Interface Design and Application信息信息学院学院STM32F103的概述的概述n内嵌跟踪模内嵌跟踪模块块(ETM)u使用使用ARM的嵌入式跟踪微宏单元的嵌入式跟踪微宏单元(ETM)。uSTM32F10xxx通通过过很很少少的的ETM引引脚脚连连接接到到外外部部跟跟踪踪端端口口分分析析(TPA)设设备备，从从CPU核核心心中中以以高高速速输输出出压压缩缩的的数数据据流流，为为开开发发人人员员提提供供了了清清晰晰的的指指令令运运行行与与数数据据流流动的信息。动的信息。uTPA设设备备可可以以通通过过USB、以以太太网网或或其其它它高高速速通通道道连连接接到到调调试试主主机机，实实时时的的指指令令和和数数据据流流向向能能够够被被调调试试主主机机上的调试软件记录下来，并按需要的格式显示出来。上的调试软件记录下来，并按需要的格式显示出来。uTPA硬硬件件可可以以从从开开发发工工具具供供应应商商处处购购得得，并并能能与与第第三三方的调试软件兼容。方的调试软件兼容。Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u144PinsEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u100PinsEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u64PinsEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapA3A3-11PE2I/OFTPE2TRACECK/ FSMC_A23A2B3-22PE3I/OFTPE3TRACED0/FSMC_A19B2C3-33PE4I/OFTPE4TRACED1/FSMC_A20B3D3-44PE5I/OFTPE5TRACED2/FSMC_A21B4E3-55PE6I/OFTPE6TRACED3/FSMC_A22C2B2C6 166VBATSVBATA1A2 C8 277PC13-TAMPER-RTCI/OPC13TAMPER-RTCB1A1B8388PC14-OSC32_INI/OPC14OSC32_INC1B1B7499PC15-OSC32_OUTI/OPC15OSC32_OUTC3-10PF0I/OFTPF0FSMC_A0C4-11PF1I/OFTPF1FSMC_A1D4-12PF2I/OFTPF2FSMC_A2E2-13PF3I/OFTPF3FSMC_A3E3-14PF4I/OFTPF4FSMC_A4E4-15PF5I/OFTPF5FSMC_A5D2C2-1016VSS_5SVSS_5D3D2-1117VDD_5SVDD_5F3-18PF6I/OPF6ADC3_IN4/FSMC_NIORDF2-19PF7I/OPF7ADC3_IN5/FSMC_NREGG3-20PF8I/OPF8ADC3_IN6/FSMC_NIOWREmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapG2-21PF9I/OPF9ADC3_IN7/FSMC_CDG1-22PF10I/OPF10ADC3_IN8/FSMC_INTRD1C1 D8 51223OSC_INIOSC_INE1D1 D7 61324OSC_OUTOOSC_OUTF1E1C7 71425NRSTI/ONRSTH1F1E881526PC0I/OPC0ADC123_IN10H2F2F891627PC1I/OPC1ADC123_IN11H3E2D6 10 1728PC2I/OPC2ADC123_IN12H4F3-11 1829PC3I/OPC3ADC123_IN13J1G1 E7 12 1930VSSASVSSAK1H1-2031VREF-SVREF-L1J1F7 -2132VREF+SVREF+M1K1 G8 13 2233VDDASVDDAJ2G2F6 14 2334 PA0-WKUP I/OPA0WKUP/USART2_CTS ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETRK2H2 E6 15 2435PA1I/OPA1USART2_RTS ADC123_IN1/ TIM5_CH2/TIM2_CH2L2J2H8 16 2536PA2I/OPA2USART2_TX/TIM5_CH3 ADC123_IN2/ TIM2_CH3 M2K2 G7 17 2637PA3I/OPA3USART2_RX/TIM5_CH4 ADC123_IN3/TIM2_CH4G4E4F5 18 2738VSS_4SVSS_4F4F4G6 19 2839VDD_4SVDD_4J3G3 H7 20 2940PA4I/OPA4SPI1_NSS/ USART2_CK DAC_OUT1/ADC12_IN4Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapK3H3 E5 21 3041PA5I/OPA5SPI1_SCK DAC_OUT2 ADC12_IN5L3J3G5 22 3142PA6I/OPA6SPI1_MISO TIM8_BKIN/ADC12_IN6 TIM3_CH1TIM1_BKINM3K3 G4 23 3243PA7I/OPA7SPI1_MOSI/ TIM8_CH1N/ADC12_IN7 TIM3_CH2TIM1_CH1NJ4G4 H6 24 3344PC4I/OPC4ADC12_IN14K4H4 H5 25 3445PC5I/OPC5ADC12_IN15L4J4H4 26 3546PB0I/OPB0ADC12_IN8/TIM3_CH3 TIM8_CH2NTIM1_CH2NM4K4F4 27 3647PB1I/OPB1ADC12_IN9/TIM3_CH4 TIM8_CH3NTIM1_CH3NJ5G5 H3 28 3748PB2I/OFTPB2/BOOT1M5-49PF11I/OFTPF11FSMC_NIOS16L5-50PF12I/OFTPF12FSMC_A6H5-51VSS_6SVSS_6G5-52VDD_6SVDD_6K5-53PF13I/OFTPF13FSMC_A7M6-54PF14I/OFTPF14FSMC_A8L6-55PF15I/OFTPF15FSMC_A9K6-56PG0I/OFTPG0FSMC_A10J6-57PG1I/OFTPG1FSMC_A11M7H5-3858PE7I/OFTPE7FSMC_D4TIM1_ETRL7J5-3959PE8I/OFTPE8FSMC_D5TIM1_CH1NK7K5-4060PE9I/OFTPE9FSMC_D6TIM1_CH1Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapH6-61VSS_7SVSS_7G6-62VDD_7SVDD_7J7G6-4163PE10I/OFTPE10FSMC_D7TIM1_CH2NH8H6-4264PE11I/OFTPE11FSMC_D8TIM1_CH2J8J6-4365PE12I/OFTPE12FSMC_D9TIM1_CH3NK8K6-4466PE13I/OFTPE13FSMC_D10TIM1_CH3L8G7-4567PE14I/OFTPE14FSMC_D11TIM1_CH4M8H7-4668PE15I/OFTPE15FSMC_D12TIM1_BKINM9J7G3 29 4769PB10I/OFTPB10I2C2_SCL/USART3_TXTIM2_CH3M10 K7F3 30 4870PB11I/OFTPB11I2C2_SDA/USART3_RXTIM2_CH4H7E7 H2 31 4971VSS_1SVSS_1G7F7H1 32 5072VDD_1SVDD_1M11 K8 G2 33 5173PB12I/OFTPB12SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK/ TIM1_BKINM12J8G1 34 5274PB13I/OFTPB13SPI2_SCK/I2S2_CK USART3_CTS/ TIM1_CH1NL11H8F2 35 5375PB14I/OFTPB14SPI2_MISO/TIM1_CH2N USART3_RTSL12G8F1 36 5476PB15I/OFTPB15SPI2_MOSI/I2S2_SD TIM1_CH3NL9K9-5577PD8I/OFTPD8FSMC_D13USART3_TXK9J9-5678PD9I/OFTPD9FSMC_D14USART3_RXJ9H9-5779PD10I/OFTPD10FSMC_D15USART3_CKH9G9-5880PD11I/OFTPD11FSMC_A16USART3_CTSEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapL10 K10-5981PD12I/OFTPD12FSMC_A17TIM4_CH1 / USART3_RTSK10 J10-6082PD13I/OFTPD13FSMC_A18TIM4_CH2G8-83VSS_8SVSS_8F8-84VDD_8SVDD_8K11 H10-6185PD14I/OFTPD14FSMC_D0TIM4_CH3K12 G10-6286PD15I/OFTPD15FSMC_D1TIM4_CH4J12-87PG2I/OFTPG2FSMC_A12J11-88PG3I/OFTPG3FSMC_A13J10-89PG4I/OFTPG4FSMC_A14H12-90PG5I/OFTPG5FSMC_A15H11-91PG6I/OFTPG6FSMC_INT2H10-92PG7I/OFTPG7FSMC_INT3G11-93PG8I/OFTPG8G10-94VSS_9SVSS_9F10-95VDD_9SVDD_9G12 F10 E1 37 6396PC6I/OFTPC6I2S2_MCK/ TIM8_CH1/SDIO_D6TIM3_CH1F12 E10 E2 38 6497PC7I/OFTPC7I2S3_MCK/ TIM8_CH2/SDIO_D7TIM3_CH2F11F9E3 39 6598PC8I/OFTPC8TIM8_CH3/SDIO_D0TIM3_CH3E11E9D1 40 6699PC9I/OFTPC9TIM8_CH4/SDIO_D1TIM3_CH4E12D9E4 41 67 100PA8I/OFTPA8USART1_CK/ TIM1_CH1/MCOEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapD12C9 D2 42 68 101PA9I/OFTPA9USART1_TX/ TIM1_CH2D11 D10 D3 43 69 102PA10I/OFTPA10USART1_RX/ TIM1_CH3C12 C10 C1 44 70 103PA11I/OFTPA11USART1_CTS/USBDM CAN_RX/TIM1_CH4B12 B10 C2 45 71 104PA12I/OFTPA12USART1_RTS/USBDP/ CAN_TX/TIM1_ETRA12 A10 D4 46 72 105PA13I/OFTJTMS-SWDIOPA13C11F8-73 106Not connectedG9E6B1 47 74 107VSS_2SVSS_2F9F6A1 48 75 108VDD_2SVDD_2A11A9B2 49 76 109PA14I/OFT JTCK-SWCLKPA14A10A8 C3 50 77 110PA15I/OFTJTDISPI3_NSS/ I2S3_WSTIM2_CH1_ETR PA15 / SPI1_NSSB11B9A2 51 78111PC10I/OFTPC10UART4_TX/SDIO_D2USART3_TXB10B8B3 52 79 112PC11I/OFTPC11UART4_RX/SDIO_D3USART3_RXC10C8 C4 53 80 113PC12I/OFTPC12UART5_TX/SDIO_CKUSART3_CKE10D8 D8 581 114PD0I/OFTOSC_INFSMC_D2CAN_RXD10E8D7 682 115PD1I/OFTOSC_OUTFSMC_D3CAN_TXE9B7A3 54 83 116PD2I/OFTPD2TIM3_ETR/UART5_RX SDIO_CMDD9C7-84 117PD3I/OFTPD3FSMC_CLKUSART2_CTSC9D7-85 118PD4I/OFTPD4FSMC_NOEUSART2_RTSB9B6-86 119PD5I/OFTPD5FSMC_NWEUSART2_TXE7-120VSS_10SVSS_10Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义PinsPin nameTypeI/OLevelMainfunction(after reset)Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapF7-121VDD_10SVDD_10A8C6-87 122PD6I/OFTPD6FSMC_NWAITUSART2_RXA9D6-88 123PD7I/OFTPD7FSMC_NE1/FSMC_NCE2USART2_CKE8-124PG9I/OFTPG9FSMC_NE2/FSMC_NCE3D8-125PG10I/OFTPG10FSMC_NCE4_1/ FSMC_NE3C8-126PG11I/OFTPG11FSMC_NCE4_2B8-127PG12I/OFTPG12FSMC_NE4D7-128PG13I/OFTPG13FSMC_A24C7-129PG14I/OFTPG14FSMC_A25E6-130VSS_11SVSS_11F6-131VDD_11SVDD_11B7-132PG15I/OFTPG15A7A7 A4 55 89 133PB3/I/OFTJTDOSPI3_SCK / I2S3_CK/PB3/TRACESWO TIM2_CH2 / SPI1_SCKA6A6B4 56 90 134PB4I/OFTNJTRSTSPI3_MISOPB4 / TIM3_CH1 SPI1_MISOB6C5 A5 57 91 135PB5I/OPB5I2C1_SMBA/ SPI3_MOSI I2S3_SDTIM3_CH2 / SPI1_MOSIC6B5B5 58 92 136PB6I/OFTPB6I2C1_SCL/ TIM4_CH1USART1_TXD6A5 C5 59 93 137PB7I/OFTPB7I2C1_SDA / FSMC_NADV / TIM4_CH2USART1_RXD5D5 A6 60 94 138BOOT0IBOOT0C5B4D5 61 95 139PB8I/OFTPB8TIM4_CH3/SDIO_D4I2C1_SCL/ CAN_RXB5A4B6 62 96 140PB9I/OFTPB9TIM4_CH4/SDIO_D5I2C1_SDA / CAN_TXEmbedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u说明说明l1.I = 输入，输入，O = 输出，输出，S = 电源，电源， HiZ = 高阻高阻l2.FT：容忍：容忍5Vl3.复位后的主功能，有些功能仅在部分型号芯片中支持。复位后的主功能，有些功能仅在部分型号芯片中支持。l4.如如果果有有几几个个外外设设共共享享一一个个I/O口口，为为了了避避免免引引脚脚之之间间的的冲冲突突，在在同同一一个个时时刻刻，通通过过外外设设时时钟钟允允许许控控制制位位（RCC外外设设时时钟钟允许寄存器），只允许一个外设有效。允许寄存器），只允许一个外设有效。PinsPin nameTypeI/OLevelMainfunction(after reset)主功能主功能Alternate functionsBGA144BGA100WLCSP64LQFP64LQFP100LQFP144DefaultRemapA5D4-97 141PE0I/OFTPE0TIM4_ETR / FSMC_NBL0A4C4-98 142PE1I/OFTPE1FSMC_NBL1E5E5A7 63 99 143VSS_3SVSS_3F5F5A8 64 100 144VDD_3SVDD_3Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u说明说明l5.PC13，PC14和和PC15引引脚脚通通过过电电源源开开关关进进行行供供电电，而而这这个个电电源源开开关关只只能能够够吸吸收收有有限限的的电电流流(3mA)。因因此此这这三三个个引引脚脚作作为为输输出出引引脚脚时时有有以以下下限限制制：在在同同一一时时间间只只有有一一个个引引脚脚能能作作为为输输出出脚脚，作作为为输输出出脚脚时时只只能能工工作作在在2MHz模模式式下下，最最大大驱驱动动负负载载为为30pF，并且不能作为电流源，并且不能作为电流源(如驱动如驱动LED)。l6.PC13，PC14和和PC15这这些些引引脚脚在在备备份份区区域域第第一一次次上上电电时时处处于于主主功功能能状状态态下下，之之后后即即使使复复位位，这这些些引引脚脚的的状状态态由由备备份份区区域域寄寄存存器器控控制制（这这些些寄寄存存器器不不会会被被主主复复位位系系统统所所复复位位）。关关于于如如何何控控制制这这些些IO口口的的具具体体信信息息，请请参参考考STM32F10xxx参参考考手手册册的电池备份区域和的电池备份区域和BKP寄存器的相关章节。寄存器的相关章节。l7.与与LQFP64的的封封装装不不同同，在在WLCSP封封装装上上没没有有PC3，但但提提供了供了VREF+引脚。引脚。Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u说明说明l8.此此类类复复用用功功能能能能够够由由软软件件配配置置到到其其他他引引脚脚上上(如如果果相相应应的的封封装装型型号号有有此此引引脚脚)，详详细细信信息息请请参参考考STM32F10xxx参参考考手手册册的复用功能的复用功能I/O章节和调试设置章节。章节和调试设置章节。l9.LQFP64封封装装的的引引脚脚5和和引引脚脚6在在芯芯片片复复位位后后默默认认配配置置为为OSC_IN和和OSC_OUT功功能能脚脚。软软件件可可以以重重新新设设置置这这两两个个引引脚脚为为PD0和和 PD1功功 能能 。 但但 对对 于于 LQFP100/BGA100封封 装装 和和LQFP144/BGA144封封装装，由由于于PD0和和PD1为为固固有有的的功功能能引引脚脚，因因此此没没有有必必要要再再由由软软件件进进行行重重映映像像设设置置。更更多多详详细细信信息息请请参参考考STM32F10xxx的复用功能的复用功能I/O章节和调试设置章节。章节和调试设置章节。l10.LPFP64封装的产品，没有封装的产品，没有FSMC功能。功能。Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性n引脚定引脚定义义u说明说明l11.译者注译者注表表中中的的引引脚脚名名称称标标注注中中出出现现的的ADC12_INx(x表表示示49或或1415之之间间的的整整 数数 )， 表表 示示 这这 个个 引引 脚脚 可可 以以 是是 ADC1_INx或或 ADC2_INx。 例例 如如 ：ADC12_IN9表表 示示 这这 个个 引引 脚脚 可可 以以 配配 置置 为为 ADC1_IN9， 也也 可可 以以 配配 置置 为为ADC2_IN9。同同样样，表表中中的的引引脚脚名名称称标标注注中中出出现现的的ADC123_INx(x表表示示03或或1013之之 间间 的的 整整 数数 )， 表表 示示 这这 个个 引引 脚脚 可可 以以 是是 ADC1_INx或或 ADC2_INx或或ADC3_INx。表表中中的的引引脚脚PA0对对应应的的复复用用功功能能中中的的TIM2_CH1_ETR，表表示示可可以以配配置置该该功功能能为为TIM2_TI1或或TIM2_ETR。同同理理，PA15对对应应的的重重映映射射复复用用功功能能的的名称名称TIM2_CH1_ETR，具有相同的意义。，具有相同的意义。Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性nFSMC引脚定引脚定义义PinsFSMCLQFP100BGA100(1)CFCF/IDE NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bitPE2A23A23YesPE3A19A19YesPE4A20A20YesPE5A21A21YesPE6A22A22YesPF0A0A0A0-PF1A1A1A1-PF2A2A2A2-PF3A3A3-PF4A4A4-PF5A5A5-PF6NIORD NIORD-PF7NREGNREG-PF8NIOWR NIOWR-PF9CDCD-PF10INTRINTR-PF11 NIOS16 NIOS16-PF12A6A6-PF13A7A7-PF14A8A8-PF15A9A9-Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性nFSMC引脚定引脚定义义PinsFSMCLQFP100BGA100(1)CFCF/IDE NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bitPG0A10A10-PG1A11-PE7D4D4D4DA4D4YesPE8D5D5D5DA5D5YesPE9D6D6D6DA6D6YesPE10D7D7D7DA7D7YesPE11D8D8D8DA8D8YesPE12D9D9D9DA9D9YesPE13D10D10D10DA10D10YesPE14D11D11D11DA11D11YesPE15D12D12D12DA12D12YesPD8D13D13D13DA13D13YesPD9D14D14D14DA14D14YesPD10D15D15D15DA15D15YesPD11A16A16CLEYesPD12A17A17ALEYesPD13A18A18YesPD14D0D0D0DA0D0YesPD15D1D1D1DA1D1YesPG2A12-PG3A13-Embedded System Interface Design and Application信息信息学院学院STM32F103的外特性的外特性nFSMC引脚定引脚定义义PinsFSMCLQFP100BGA100(1)CFCF/IDE NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bitPG4A14-PG5A15-PG6INT2-PG7INT3-PD0D2D2D2DA2D2YesPD1D3D3D3DA3D3YesPD3CLKCLKYesPD4NOENOENOENOENOEYesPD5NWENWENWENWENWEYesPD6NWAIT NWAITNWAITNWAITNWAITYesPD7NE1NE1NCE2YesPG9NE2NE2NCE3-PG10 NCE4_1 NCE4_1NE3NE3-PG11 NCE4_2 NCE4_2-PG12NE4NE4-PG13A24A24-PG14A25A25-PB7NADVNADVYesPE0NBL0NBL0YesPE1NBL1NBL1YesEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性nSTM32F103系系统统架构架构Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性nSTM32F103系系统统架构架构uFour masters:四个主控器四个主控器lCortex-M3 core, DCode bus(D-bus) and System bus (S-bus)lGP-DMA1 & 2 (general-purpose DMA)uFour slaves:四个从单元四个从单元lInternal SRAMlInternal Flash memorylFSMC(Flexible static memory controller)lAHB to APB bridges (AHB2APBx), which connect all the APB peripheralsEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射uSTM32的存储器组织的存储器组织l程程序序存存储储器器、数数据据存存储储器器、寄寄存存器器和和输输入入输输出出端端口口被被组组织织在在同一个同一个4GB的线性地址空间内。的线性地址空间内。l可访问的存储器被分为可访问的存储器被分为8个个512MB的块（的块（BANK）。）。l数数据据字字节节以以小小端端格格式式存存放放在在存存储储器器中中，也也即即一一个个字字的的最最低低有有效字节被存放在该字的最低地址字节中。效字节被存放在该字的最低地址字节中。l片内集成的片内集成的Flash、SRAM被映射到如下的地址空间中。被映射到如下的地址空间中。 Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射uSTM32的存储器组织的存储器组织lSRAM最高达最高达64KB，地址范围，地址范围0x200000000x2000FFFFlFLASH：由：由3个部分组成：个部分组成：Main Block, Information Block, System Memory；lMain Block用用 于于 存存 放放 用用 户户 程程 序序 ， 最最 高高 达达 512KB， 地地 址址 范范 围围0x080000000x807FFFFF。lInformation Block包括包括System Memory和和Option Bytes两个部分。两个部分。System Memory地地址址范范围围0x1FFFF F000 0X1FFFF F7FF共共计计2KB，用于存放通过，用于存放通过UART1进行进行ISP编程的编程的BOOTLOADER。Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射u8个个BANKlICode=Block0lISRAM=Block1lIPrph=Block2lExt. RAM=Bank3+Block4lExt. Device=Block5+Block6lPPBI/E+Vend=Block7Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射图图uBlock3/4/5Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射图图uBlock2u外设寄存器外设寄存器Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射器影射图图uBlock0/1Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射表器影射表0xFFFF FFFF 512-Mbyte block 7 ReservedReservedCortex-M3s0xE000 0000internal peripheral0xDFFF FFFF 512-MbyteReservedReservedblock 60xC000 0000Not used0xBFFF FFFF 512-MbyteReservedReservedblock 50xA000 0000FSMC register0x9FFF FFFF 512-MbyteReserved0xA000 1000 - 0xBFFF FFFFblock 40x8000 0000FSMC bank 3&4FSMC register0xA000 0000 - 0xA000 0FFF0x7FFF FFFF 512-MbyteFSMC bank4 PCCARD0x9000 0000 - 0x9FFF FFFFblock 3FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFFFSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFFFSMC bank1 NOR/PSRAM 40x6C00 0000 - 0x6FFF FFFFFSMC bank1 NOR/PSRAM 30x6800 0000 - 0x6BFF FFFFFSMC bank1 NOR/PSRAM 20x6400 0000 - 0x67FF FFFF0x6000 0000FSMC bank1& 2FSMC bank1 NOR/PSRAM 10x6000 0000 - 0x63FF FFFF0x5FFF FFFFEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射表器影射表0x6000 00000x5FFF FFFF 512-MbyteReserved0x4002 4400 - 0x5FFF FFFFblock 2(1)CRC0x4002 3000 - 0x4002 33FFReserved0x4002 2400 - 0x4002 2FFFFlash interface0x4002 2000 - 0x4002 23FFReserved0x4002 1400 - 0x4002 1FFFRCC0x4002 1000 - 0x4002 13FFReserved0x4002 0400 - 0x4002 0FFFDMA20x4002 0400 - 0x4002 07FFDMA10x4002 0000 - 0x4002 03FFReserved0x4001 8400 - 0x4001 FFFFSDIO0x4001 8000 - 0x4001 83FFReserved0x4001 400 - 0x4001 7FFFADC30x4001 3C00 - 0x4001 3FFFUSART10x4001 3800 - 0x4001 3BFFTIM80x4001 3400 - 0x4001 37FFSPI10x4001 3000 - 0x4001 33FFTIM10x4001 2C00 - 0x4001 2FFFADC20x4001 2800 - 0x4001 2BFFADC10x4001 2400 - 0x4001 27FFPort G0x4001 2000 - 0x4001 23FF0x4001 1C00 Port F0x4001 1C00 - 0x4001 1FFF0x4001 1BFFEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射表器影射表0x4001 1C00 0x4001 1BFFPort E0x4001 1800 - 0x4001 1BFFblock 2(2)Port D0x4001 1400 - 0x4001 17FFPort C0x4001 1000 - 0x4001 13FFPort B0x4001 0C00 - 0x4001 0FFFPort A0x4001 0800 - 0x4001 0BFFEXTI0x4001 0400 - 0x4001 07FFAFIO0x4001 0000 - 0x4001 03FFReserved0x4000 7800 - 0x4000 FFFFDAC0x4000 7400 - 0x4000 77FFPWR0x4000 7000 - 0x4000 73FFBKP0x4000 6C00 - 0x4000 6FFFReserved0x4000 6800 - 0x4000 6BFFBxCAN0x4000 6400 - 0x4000 67FFShared USB/CAN SRAM 512B 0x4000 6000 - 0x4000 63FFUSB registers0x4000 5C00 - 0x4000 5FFFI2C20x4000 5800 - 0x4000 5BFFI2C10x4000 5400 - 0x4000 57FFUART50x4000 5000 - 0x4000 53FFUART40x4000 4C00 - 0x4000 4FFF0x4000 4800 USART30x4000 4800 - 0x4000 4BFF0x4000 47FFEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射表器影射表0x4000 4800 0x4000 47FFUSART20x4000 4400 - 0x4000 47FFblock 2(3)Reserved0x4000 4000 - 0x4000 43FFSPI3/I2S30x4000 3C00 - 0x4000 3FFFSPI2/I2S20x4000 3800 - 0x4000 3BFFReserved0x4000 3400 - 0x4000 37FFIWDG0x4000 3000 - 0x4000 33FFWWDG0x4000 2C00 - 0x4000 2FFFRTC0x4000 2800 - 0x4000 2BFFReserved0x4000 1800 - 0x4000 27FFTIM70x4000 1400 - 0x4000 17FFTIM60x4000 1000 - 0x4000 13FFTIM50x4000 0C00 - 0x4000 0FFFTIM40x4000 0800 - 0x4000 0BFFTIM30x4000 0400 - 0x4000 07FF0x4000 0000PeripheralsTIM20x4000 0000 - 0x4000 03FF0x3FFF FFFFEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n存存储储器影射表器影射表0x4000 00000x3FFF FFFF 512-MbyteReserved0x2001 0000 0x3FFF FFFFblock 1SRAM(64 KB aliased by bit-banding)0x2000 FFFF0x2000 00000x2000 0000SRAM0x1FFF FFFF 512-MbyteOption Bytes0x1FFF F800 - 0x1FFF F80Fblock 0System memory0x1FFF F000- 0x1FFF F7FFReserved0x0808 0000 - 0x1FFF EFFFFlash0x0800 0000 - 0x0807 FFFFReserved0x0008 0000 - 0x07FF FFFFAliased to Flash or system0x0007 FFFF0x0000 0000Codememory depend on BOOT pins 0x0000 0000Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n寄存器影射寄存器影射uBLOCK2-片内片内SFRBoundary address Peripheral Bus 0x5000 0000 - 0x5000 03FF USB OTG FS 0x4003 0000 - 0x4FFF FFFF Reserved AHB 0x4002 8000 - 0x4002 9FFF Ethernet 0x4002 3400 - 0x4002 7FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2000 - 0x4002 23FF Flash memory interface 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF Reset and clock control RCC AHB 0x4002 0800 - 0x4002 0FFF Reserved 0x4002 0400 - 0x4002 07FF DMA2 0x4002 0000 - 0x4002 03FF DMA1 0x4001 8400 - 0x4001 7FFF Reserved 0x4001 8000 - 0x4001 83FF SDIO 0x4001 4000 - 0x4001 7FFF Reserved 0x4001 3C00 - 0x4001 3FFF ADC3 0x4001 3800 - 0x4001 3BFF USART1 Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n寄存器影射寄存器影射uBLOCK2-片内片内SFRBoundary address Peripheral Bus 0x4001 3400 - 0x4001 37FF TIM8 timer 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF TIM1 timer 0x4001 2800 - 0x4001 2BFF ADC2 0x4001 2400 - 0x4001 27FF ADC1 0x4001 2000 - 0x4001 23FF GPIO Port G APB2 0x4001 1C00 - 0x4001 1FFF GPIO Port F 0x4001 1800 - 0x4001 1BFF GPIO Port E 0x4001 1400 - 0x4001 17FF GPIO Port D 0x4001 1000 - 0x4001 13FF GPIO Port C 0x4001 0C00 - 0x4001 0FFF GPIO Port B 0x4001 0800 - 0x4001 0BFF GPIO Port A 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF DAC Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n寄存器影射寄存器影射uBLOCK2-片内片内SFRBoundary address Peripheral Bus 0x4000 7000 - 0x4000 73FF Power control PWR 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF bxCAN1 0x4000 6800 - 0x4000 6BFF bxCAN2 0x4000 6000 - 0x4000 63FF Shared USB/CAN SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF USB device FS registers 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 APB1 0x4000 4000 - 0x4000 3FFF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3/I2S 0x4000 3800 - 0x4000 3BFF SPI2/I2S Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n寄存器影射寄存器影射uBLOCK2-片内片内SFRBoundary address Peripheral Bus 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) 0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) 0x4000 2800 - 0x4000 2BFF RTC 0x4000 1800 - 0x4000 27FF Reserved 0x4000 1400 - 0x4000 17FF TIM7 timer 0x4000 1000 - 0x4000 13FF TIM6 timer 0x4000 0C00 - 0x4000 0FFF TIM5 timer 0x4000 0800 - 0x4000 0BFF TIM4 timer 0x4000 0400 - 0x4000 07FF TIM3 timer 0x4000 0000 - 0x4000 03FF TIM2 timer Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内SRAMuSTM32F10xxx内置内置64KB的静态的静态SRAM。u它可以以字节、半字它可以以字节、半字(16位位)或全字或全字(32位位)访问。访问。uSRAM的起始地址是的起始地址是0x2000 0000。Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内位段片内位段uCortex-M3存存储储器器映映像像包包括括两两个个位位段段(bit-band)区区。这这两两个个位位段段区区将将别别名名存存储储器器区区中中的的一一个个字字映映射射到到位位段段存存储储器器区区的的一一个个位位；在在别别名名存存储储区区写写入入一一个个字字具具有对位段区的目标位执行读有对位段区的目标位执行读-改改-写操作的相同效果。写操作的相同效果。uSTM32F10xxx的的外外设设寄寄存存器器和和SRAM都都被被映映射射到到一一个位段区里，这允许执行单一的位段的写和读操作。个位段区里，这允许执行单一的位段的写和读操作。u映射公式给出了别名区中的字与位带区的关系：映射公式给出了别名区中的字与位带区的关系：bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number 4)bit_word_addr是别名存储器区中字的地址，它映射到某个目标位。是别名存储器区中字的地址，它映射到某个目标位。bit_band_base是别名区的起始地址。是别名区的起始地址。byte_offset是包含目标位的字节在位段里的序号是包含目标位的字节在位段里的序号bit_number是目标位所在位置是目标位所在位置(0-31)Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内位段片内位段u实例：实例：l映射别名区中映射别名区中SRAM地址为地址为0x20000300的字节中的位的字节中的位2：0x22000000 + (0x300*32) + (2*4) = 0x22006008l对对0x22006008地地址址的的写写操操作作与与对对SRAM中中地地址址0x20000300字节的位字节的位2执行读执行读-改改-写操作有着相同的效果。写操作有着相同的效果。l读读0x22006008地地址址返返回回SRAM中中地地址址0x20000300字字节节的的位位2的值的值(0x01 或或 0x00)。u参参考考Cortex-M3技技术术参参考考手手册册了了解解更更多多有有关关位位段的信息。段的信息。Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu高性能的闪存模块有以下的主要特性高性能的闪存模块有以下的主要特性l高高达达512K字字节节闪闪存存存存储储器器结结构构：闪闪存存存存储储器器有有主主存存储储块块和和信信息块组成。息块组成。l主存储块主存储块主主存存储储块块容容量量：小小容容量量产产品品主主存存储储块块为为4Kbx64位位，每每个个主主存存储储块块划划分分为为32个个1K字节的页。字节的页。中中容容量量产产品品主主存存储储块块为为16Kbx64位位，每每个个主主存存储储块块划划分分为为128个个1K字字节的页。节的页。大大容容量量产产品品主主存存储储块块为为64Kbx64位位，每每个个主主存存储储块块划划分分为为256个个2K字字节的页。节的页。l信息块信息块信信息息块块为为258x64位位，每每个个信信息息块块划划分分为为一一个个2K字字节节的的页页和和一一个个16字字节节的页。的页。Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu闪存存储器接口的特性为闪存存储器接口的特性为l带预取缓冲器的读接口带预取缓冲器的读接口(每字为每字为2x64位位)l选择字节加载器选择字节加载器l闪存编程闪存编程/擦除操作擦除操作l访问访问/写保护写保护u闪存模块的组织分了闪存模块的组织分了l小容量小容量1632KBl中容量中容量64128KBl大容量大容量256512KBEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu闪存模块的组织闪存模块的组织l小容量产品小容量产品Block Name Base addresses Size(bytes)Mainmemory Page 0 0x0800 0000 - 0x0800 03FF 1 KbytesPage 1 0x0800 0400 - 0x0800 07FF 1 KbytesPage 2 0x0800 0800 - 0x0800 0BFF 1 KbytesPage 3 0x0800 0C00 - 0x0800 0FFF1 KbytesPage 4 0x0800 1000 - 0x0800 13FF 1 Kbytes. . . . . . . . Page 31 0x0800 7C00 - 0x0800 7FFF1 Kbytes Informationblock System memory0x1FFF F000 - 0x1FFF F7FF2 Kbytes Option Bytes 0x1FFF F800 - 0x1FFF F80F16bytesEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu闪存模块的组织闪存模块的组织l小容量产品小容量产品(C)Block Name Base addresses SizeFlashmemoryinterfaceregistersFLASH_ACR0x4002 2000 - 0x4002 20034BFLASH_KEYR0x4002 2004 - 0x4002 20074BFLASH_OPTKEYR0x4002 2008 - 0x4002 200B4BFLASH_SR0x4002 200C - 0x4002 200F4BFLASH_CR0x4002 2010 - 0x4002 20134BFLASH_AR0x4002 2014 - 0x4002 20174BReserved0x4002 2018 - 0x4002 201B4BFLASH_OBR0x4002 201C - 0x4002 201F4BFLASH_WRPR 0x4002 2020 - 0x4002 20234BEmbedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu闪存读取闪存读取l闪闪存存的的指指令令和和数数据据访访问问是是通通过过AHB总总线线完完成成的的。预预取取模模块块是是用用于于通通过过ICode总总线线读读取取指指令令的的。仲仲裁裁是是作作用用在在闪闪存存接接口口，并并且且DCode总线上的数据访问优先。总线上的数据访问优先。l读访问可以有以下配置选项：读访问可以有以下配置选项：等待时间：可以随时更改的用于读取操作的等待状态的数量。等待时间：可以随时更改的用于读取操作的等待状态的数量。预预取取缓缓冲冲区区(2个个64位位)：在在每每一一次次复复位位以以后后被被自自动动打打开开，由由于于每每个个缓缓冲冲区区的的大大小小(64位位)与与闪闪存存的的带带宽宽相相同同，因因此此只只通通过过需需一一次次读读闪闪存存的的操操作作即即可可更更新新整整个个缓缓冲冲区区的的内内容容。由由于于预预取取缓缓冲冲区区的的存存在在，CPU可可以以工工作作在在更更高高的的主主频频。CPU每每次次取取指指最最多多为为32位位的的字字，取取一一条条指指令令时时，下下一一条条指指令令已已经在缓冲区中等待。经在缓冲区中等待。半周期：用于功耗优化。半周期：用于功耗优化。l注：注：1.当当AHB预分频系数不为预分频系数不为1时，必须置预取缓冲区处于开启状态。时，必须置预取缓冲区处于开启状态。Embedded System Interface Design and Application信息信息学院学院STM32F103的内特性的内特性n片内片内FLASHu闪存读取闪存读取l注：注：2.这这些些选选项项应应与与闪闪存存存存储储器器的的访访问问时时间间一一起起使使用用。等等待待周周期期体体现现了了系系统时钟统时钟(SYSCLK)频率与闪存访问时间的关系：频率与闪存访问时间的关系：0等待周期，当等待周期，当 0 SYSCLK 24MHz1等待周期，当等待周期，当 24MHz SYSCLK 48MHz2等待周期，当等待周期，当 48MHz CR |= (uint32_t)0x00000001; RCC-CFGR &= (uint32_t)0xF8FF0000; RCC-CR &= (uint32_t)0xFEF6FFFF; RCC-CR &= (uint32_t)0xFFFBFFFF; RCC-CFGR &= (uint32_t)0xFF80FFFF; RCC-CIR = 0x009F0000; SetSysClock();Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu固件函数固件函数lRV31LIBSTSTM32F10xstm32f10x_rcc.c函数名函数名 描述描述 RCC_DeInit 复位复位RCC外外设设寄存器寄存器为为默默认值认值. RCC_HSEConfig 配置外部高速振配置外部高速振荡荡器器 (HSE). RCC_WaitForHSEStartUp 等待等待 HSE 启启动动. RCC_AdjustHSICalibrationValue 调节调节内部高速振内部高速振荡荡器器 (HSI) 校正校正值值. RCC_HSICmd 允允许许或禁止内部高速振或禁止内部高速振荡荡器器 (HSI). RCC_PLLConfig 配置配置PLL时钟时钟源和倍源和倍频频. RCC_PLLCmd 允允许许或禁止或禁止 PLL. RCC_SYSCLKConfig 配置系配置系统时钟统时钟 (SYSCLK). RCC_GetSYSCLKSource 返回系返回系统时钟统时钟源源. RCC_HCLKConfig 配置配置 AHB 时钟时钟 (HCLK). RCC_PCLK1Config 配置低速配置低速 APB 时钟时钟 (PCLK1). RCC_PCLK2Config 配置高速配置高速 APB 时钟时钟 (PCLK2). RCC_ITConfig 允允许许或禁止指定或禁止指定 RCC 中断中断. RCC_USBCLKConfig 配置配置 USB 时钟时钟 (USBCLK). RCC_ADCCLKConfig 配置配置 ADC 时钟时钟 (ADCCLK). RCC_LSEConfig 配置外部低速振配置外部低速振荡荡器器 (LSE). Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu固件函数固件函数lRV31LIBSTSTM32F10xstm32f10x_rcc.c函数名函数名 描述描述 RCC_LSICmd 允允许许或禁止外部低速振或禁止外部低速振荡荡器器(LSI). RCC_RTCCLKConfig 配置配置 RTC 时钟时钟 (RTCCLK). RCC_RTCCLKCmd 允允许许或禁止或禁止 RTC 时钟时钟 RCC_GetClocksFreq 返回不同的返回不同的时钟频时钟频率率. RCC_AHBPeriphClockCmd 允允许许或禁止或禁止 AHB 外外设时钟设时钟. RCC_APB2PeriphClockCmd 允允许许或禁止高速或禁止高速 APB (APB2) 外外设时钟设时钟. RCC_APB1PeriphClockCmd 允允许许或禁止低速或禁止低速 APB (APB1) 外外设时钟设时钟. RCC_APB2PeriphResetCmd 强强制或解除高速制或解除高速 APB (APB2) 外外设设复位复位. RCC_APB1PeriphResetCmd 强强制或解除低速制或解除低速 APB (APB1) 外外设设复位复位. RCC_BackupResetCmd 强强制或解除制或解除备备份域复位份域复位. RCC_ClockSecuritySystemCmd 允允许许或禁止或禁止时钟时钟安全系安全系统统. RCC_MCOConfig 选择时钟选择时钟源源输输出到出到 MCO 引脚引脚. RCC_GetFlagStatus 检查检查 RCC 标记标记是否是否设设置置. RCC_ClearFlag 清除清除 RCC 复位复位标记标记. RCC_GetITStatus 检查检查 RCC 中断是否中断是否产产生生. RCC_ClearITPendingBit 清除清除 RCC 中断中断请请求位求位. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化/以下时钟配置为最高性能以下时钟配置为最高性能void SystemClockInit(void)/设置设置flash等待周期为等待周期为2，否则设置为，否则设置为72M系统时钟时就会跑飞系统时钟时就会跑飞FLASH_ACR=0x32; pbRCC_CR-HSEON=1; /使能外部高速时钟使能外部高速时钟while(!(pbRCC_CR-HSERDY); /等待外部高速时钟稳定等待外部高速时钟稳定pbRCC_CFGR-MCO=0; /MCO无时钟输出无时钟输出 pbRCC_CFGR-USBPRE=1; /USB时钟时钟1.5分频分频pbRCC_CFGR-PLLMUL=9-2; /PLL倍频设置为倍频设置为9倍倍*8M=72M)pbRCC_CFGR-PLLXTPRE=0; /HSE不分频不分频pbRCC_CFGR-PLLSRC=1; /HSE选作做为选作做为PLL时钟源输入时钟源输入pbRCC_CFGR-ADCPRE=0; /ADC时钟时钟2分频分频Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化void SystemClockInit(void)pbRCC_CFGR-PPRE2=1+6; /APB2设置为设置为1分频分频pbRCC_CFGR-PPRE1=2+6; /APB1设置为设置为2分频分频pbRCC_CFGR-HPRE=0; /AHB无分频无分频pbRCC_CR-PLLON=1; /启动启动PLLwhile(!(pbRCC_CR-PLLRDY); /等待等待PLL稳定稳定pbRCC_CFGR-SW=2; /选择选择PLL输出为时钟源输出为时钟源/pbRCC_AHBENR-SRAMEN=1;/pbRCC_AHBENR-FLITFEN=1;/IO口第二功能时钟使能口第二功能时钟使能pbRCC_APB2ENR-AFIOEN=1;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化void SystemClockInit(void)/各通用各通用IO口时钟使能口时钟使能pbRCC_APB2ENR-IOPAEN=1;pbRCC_APB2ENR-IOPBEN=1;pbRCC_APB2ENR-IOPCEN=1;pbRCC_APB2ENR-IOPDEN=1;pbRCC_APB2ENR-IOPEEN=1;/ADC时钟使能时钟使能pbRCC_APB2ENR-ADC1EN=1;pbRCC_APB2ENR-ADC2EN=1;/定时器定时器1时钟使能时钟使能pbRCC_APB2ENR-TIM1EN=1;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化void SystemClockInit(void)/SPI1时钟使能时钟使能pbRCC_APB2ENR-SPI1EN=1;/串口串口1时钟使能时钟使能pbRCC_APB2ENR-USART1EN=1;/定时器定时器2、3、4时钟使能时钟使能pbRCC_APB1ENR-TIM2EN=1;pbRCC_APB1ENR-TIM3EN=1;pbRCC_APB1ENR-TIM4EN=1;/窗口看门狗时钟不使能窗口看门狗时钟不使能pbRCC_APB1ENR-WWDGEN=0;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化void SystemClockInit(void)/SPI2时钟使能时钟使能pbRCC_APB1ENR-SPI2EN=1;/串口串口2、3时钟使能时钟使能pbRCC_APB1ENR-USART2EN=1;pbRCC_APB1ENR-USART3EN=1;/I2C1、2时钟使能时钟使能pbRCC_APB1ENR-I2C1EN=1;pbRCC_APB1ENR-I2C2EN=1;/USB时钟使能时钟使能pbRCC_APB1ENR-USBEN=1;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu系统时钟初始化系统时钟初始化void SystemClockInit(void)/CAN时钟使能时钟使能pbRCC_APB1ENR-CANEN=1;/备份接口时钟使能备份接口时钟使能pbRCC_APB1ENR-BKPEN=1;/电源接口时钟使能电源接口时钟使能pbRCC_APB1ENR-PWREN=1;/外部低速时钟启动外部低速时钟启动pbRCC_BDCR-LSEON=1;pbRCC_BDCR-LSEBYP=0;pbRCC_BDCR-RTCSEL=1; /选择外部时钟为选择外部时钟为RTC时钟时钟Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟l设置时钟流程设置时钟流程l1、将、将RCC寄存器重新设置为默认值寄存器重新设置为默认值RCC_DeInit()l2、打开外部高速时钟晶振、打开外部高速时钟晶振HSE RCC_HSEConfig(RCC_HSE_ON);l3、等待外部高速时钟晶振工作、等待外部高速时钟晶振工作HSEStartUpStatus = RCC_WaitForHSEStartUp();l4、设置、设置AHB时钟时钟RCC_HCLKConfig;l5、设置高速、设置高速AHB时钟时钟RCC_PCLK2Config;l6、设置低速速、设置低速速AHB时钟时钟RCC_PCLK1Configl7、设置、设置PLL RCC_PLLConfigl8、打开、打开PLL RCC_PLLCmd(ENABLE);Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟l设置时钟流程设置时钟流程l9、等待、等待PLL工作工作while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) = RESET) l10、设置系统时钟、设置系统时钟RCC_SYSCLKConfigl11、判断是否、判断是否PLL是系统时钟是系统时钟while(RCC_GetSYSCLKSource() != 0x08)l12、打开要使用的外设时钟、打开要使用的外设时钟RCC_APB2PeriphClockCmd()/ RCC_APB1PeriphClockCmd()Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟static void RCC_Configuration(void)/In main.c/* 这里是重置了这里是重置了RCC的设置，类似寄存器复位的设置，类似寄存器复位 */RCC_DeInit();/* 使能外部高速晶振使能外部高速晶振 */RCC_HSEConfig(RCC_HSE_ON);/* 等待高速晶振稳定等待高速晶振稳定 */HSEStartUpStatus = RCC_WaitForHSEStartUp();if (HSEStartUpStatus = SUCCESS)/if-begin/* 使能使能flash预读取缓冲区预读取缓冲区 */FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);/* 令令Flash处于等待状态，处于等待状态，2是针对高频时钟的是针对高频时钟的 */FLASH_SetLatency(FLASH_Latency_2);Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟static void RCC_Configuration(void)/* HCLK = SYSCLK 设置高速总线时钟设置高速总线时钟=系统时钟系统时钟*/RCC_HCLKConfig(RCC_SYSCLK_Div1);/* PCLK2 = HCLK 设置低速总线设置低速总线2时钟时钟=高速总线时钟高速总线时钟*/RCC_PCLK2Config(RCC_HCLK_Div1);/* PCLK1 = HCLK/2 设置低速总线设置低速总线1的时钟的时钟=高速时钟的二分频高速时钟的二分频*/RCC_PCLK1Config(RCC_HCLK_Div2);/* ADCCLK = PCLK2/6设置设置ADC外设时钟外设时钟=低速总线低速总线2时钟的六分频时钟的六分频*/RCC_ADCCLKConfig(RCC_PCLK2_Div6);/* Enable Prefetch Buffer */FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟static void RCC_Configuration(void)/* 利用锁相环讲外部利用锁相环讲外部8Mhz晶振晶振9倍频到倍频到72Mhz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); /* Enable PLL 使能锁相环使能锁相环*/RCC_PLLCmd(ENABLE); /* Wait till PLL is ready 等待锁相环输出稳定等待锁相环输出稳定*/while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) = RESET)/* 将锁相环输出设置为系统时钟将锁相环输出设置为系统时钟 */RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);/* 等待校验成功等待校验成功*/while (RCC_GetSYSCLKSource() != 0x08) /if-endEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟static void RCC_Configuration(void)/* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */使使能能外外围围接接口口总总线线时时钟钟，注注意意各各外外设设的的隶隶属属情情况况，不不同同芯芯片片的的分分配配不不同，到时候查手册就可以同，到时候查手册就可以RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | RCC_APB2Periph_AFIO, ENABLE);Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnRCCu使用使用HSE=8Mhz晶振用晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟l8Mhz的晶振用的晶振用PLL倍频倍频9倍形成倍形成72Mhz时钟时钟由由上上述述程程序序可可以以看看出出系系统统时时钟钟的的设设定定是是比比较较复复杂杂的的，外外设设越越多多，需需要要考考虑虑的的因因素素就就越越多多。同同时时这这种种设设定定也也是是有有规规律律可可循循的的，设设定定参参数数也也是是有有顺顺序序规规范范的的，这这是是应应当当注注意意的的。例例如如，PLL的的设设定定需需要要在在使使能能之之前前，一一旦旦PLL使能后参数不可更改。使能后参数不可更改。经经此此设设置置后后，由由于于电电路路板板上上是是8Mhz晶晶振振，所所以以系系统统时时钟钟为为72Mhz，高高速速总总线线和和低低速速总总线线2都都为为72Mhz，低低速速总总线线1为为36Mhz，ADC时时钟钟为为12Mhz，USB时钟经过时钟经过1.5分频设置就可以实现分频设置就可以实现48Mhz的数据传输。的数据传输。一一般般性性的的时时钟钟设设置置需需要要先先考考虑虑系系统统时时钟钟的的来来源源，是是内内部部RC还还是是外外部部晶晶振振还还是是外外部部的的振振荡荡器器，是是否否需需要要PLL。然然后后考考虑虑内内部部总总线线和和外外部部总总线线，最最后后考考虑虑外外设设的的时时钟钟信信号号。遵遵从从先先倍倍频频作作为为CPU时时钟钟，然然后后在在由由内内向向外外分分频频，下级迁就上级的原则有点儿类似下级迁就上级的原则有点儿类似PCB制图的规范化要求，在这里也一样。制图的规范化要求，在这里也一样。Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuNVIC register mapuThe NVIC space is split as follows:l0xE000E000-0xE000E00F:Interrupt Type Registerl0xE000E010-0xE000E0FF:System Timerl0xE000E100-0xE000ECFF:NVICl0xE000ED00-0xE000ED8F:System Control Block: CPUID System control, configuration, and status Fault reportingl0xE000EF00-0xE000EF0F:Software Trigger Exception Registerl0xE000EFD0-0xE000EFFF:ID space.Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICu中断寄存器：首地址中断寄存器：首地址0xE000E100Name of registerTypeAddressReset valueIrq 0 to 31 Set Enable RegisterRead/write 0xE000E100 0x00000000. . . . . . . . .Irq 224 to 239 Set Enable RegisterRead/write 0xE000E11C 0x00000000Irq 0 to 31 Clear Enable RegisterRead/write 0xE000E180 0x00000000. . . . . . . . .Irq 224 to 239 Clear Enable RegisterRead/write 0xE000E19C 0x00000000Irq 0 to 31 Set Pending RegisterRead/write 0xE000E200 0x00000000. . . . . . . . .Irq 224 to 239 Set Pending RegisterRead/write 0xE000E21C 0x00000000Irq 0 to 31 Clear Pending RegisterRead/write 0xE000E280 0x00000000. . . . . . . . .Irq 224 to 239 Clear Pending Register Read/write 0xE000E29C 0x00000000Irq 0 to 31 Active Bit RegisterRead-only0xE000E300 0x00000000. . . . . . . . .Irq 224 to 239 Active Bit RegisterRead-only0xE000E31C 0x00000000Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICu特性寄存器：首地址特性寄存器：首地址0xE000ED00Name of registerTypeAddressReset valueCPUID Base RegisterRead-only0xE000ED00 0x412FC230Interrupt Control State RegisterRead/write or read-only0xE000ED04 0x00000000Vector Table Offset RegisterRead/write0xE000ED08 0x00000000Application Interrupt/Reset Control Register Read/write0xE000ED0C 0x00000000System Control RegisterRead/write0xE000ED10 0x00000000Configuration Control RegisterRead/write0xE000ED14 0x00000200System Handlers 4-7 Priority RegisterRead/write0xE000ED18 0x00000000System Handlers 8-11 Priority RegisterRead/write0xE000ED1C 0x00000000System Handlers 12-15 Priority RegisterRead/write0xE000ED20 0x00000000System Handler Control and State RegisterRead/write0xE000ED24 0x00000000Configurable Fault Status RegistersRead/write0xE000ED28 0x00000000Hard Fault Status RegisterRead/write0xE000ED2C 0x00000000Debug Fault Status RegisterRead/write0xE000ED30 0x00000000Mem Manage Address RegisterRead/write0xE000ED34 UnpredictableBus Fault Address RegisterRead/write0xE000ED38 UnpredictableAuxiliary Fault Status RegisterRead/write0xE000ED3C 0x00000000Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuThe NVIC_TypeDef is in stm32f10x_map.htypedef structvu32 ISER2;u32 RESERVED030;vu32 ICER2;u32 RSERVED130;vu32 ISPR2;u32 RESERVED230;vu32 ICPR2;u32 RESERVED330;vu32 IABR2;u32 RESERVED462;vu32 IPR11; NVIC_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuThe NVIC_TypeDef is in stm32f10x_map.htypedef structvuc32 CPUID;vu32 ICSR;vu32 VTOR;vu32 AIRCR;vu32 SCR;vu32 CCR;vu32 SHPR3;vu32 SHCSR;vu32 CFSR;vu32 HFSR;vu32 DFSR;vu32 MMFAR;vu32 BFAR;vu32 AFSR; SCB_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuNVIC peripheral is in stm32f10x_map.h:#define SCS_BASE (u32)0xE000E000)#define NVIC_BASE (SCS_BASE + 0x0100)#define SCB_BASE (SCS_BASE + 0x0D00).#ifndef DEBUG.#ifdef _NVIC#define NVIC (NVIC_TypeDef *) NVIC_BASE)#define SCB (SCB_TypeDef *) SCB_BASE)#endif /*_NVIC */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuNVIC peripheral is in stm32f10x_map.h:.#else /* DEBUG */.#ifdef _NVICEXT NVIC_TypeDef *NVIC;EXT SCB_TypeDef *SCB;#endif /*_NVIC */.#endifEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuNVIC peripheral is in stm32f10x_map.h:lWhen using the Debug mode, NVIC and SCB pointers are initialized in stm32f10x_lib.c file:#ifdef _NVICNVIC = (NVIC_TypeDef *) NVIC_BASE;SCB = (SCB_TypeDef *) SCB_BASE;#endif /*_NVIC */To access the NVIC registers, _NVIC must be defined in stm32f10x_conf.h, as follows:#define _NVICEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuFirmware library functionsFunction name Description NVIC_DeInit Resets the NVIC peripheral registers to their default reset values. NVIC_SCBDeInit Resets the SCB peripheral registers to their default reset values. NVIC_PriorityGroupConfig Configures the priority grouping: pre-emption priority and subpriority. NVIC_Init Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. NVIC_StructInit Fills each NVIC_InitStruct member with its default value. NVIC_SETPRIMASK Enables the PRIMASK priority: Raises the execution priority to 0. NVIC_RESETPRIMASK Disables the PRIMASK priority. NVIC_SETFAULTMASK Enables the FAULTMASK priority: Raises the execution priority to -1. NVIC_RESETFAULTMASK Disables the FAULTMASK priority. NVIC_BASEPRICONFIG The execution priority can be changed from 15 (lowest configurable priority) to 1. Writing 0 will disable the execution priority mask. NVIC_GetBASEPRI Returns the BASEPRI mask value. NVIC_DeInit Resets the NVIC peripheral registers to their default reset values. NVIC_SCBDeInit Resets the SCB peripheral registers to their default reset values. NVIC_PriorityGroupConfig Configures the priority grouping: pre-emption priority and subpriority. NVIC_Init Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuFirmware library functionsFunction name Description NVIC_StructInit Fills each NVIC_InitStruct member with its default value. NVIC_SETPRIMASK Enables the PRIMASK priority: Raises the execution priority to 0. NVIC_RESETPRIMASK Disables the PRIMASK priority. NVIC_SETFAULTMASK Enables the FAULTMASK priority: Raises the execution priority to -1. NVIC_RESETFAULTMASK Disables the FAULTMASK priority. NVIC_BASEPRICONFIG The execution priority can be changed from 15 (lowest configurable priority) to 1. Writing 0 will disable the execution priority mask. NVIC_GetBASEPRI Returns the BASEPRI mask value. NVIC_GetCurrentPendingIRQChannel Returns the current pending served IRQ channel identifier. NVIC_GetIRQChannelPendingBitStatus Checks whether the specified IRQ Channel pending bit is set or not. NVIC_SetIRQChannelPendingBit Sets the NVIC interrupt pending bits. NVIC_ClearIRQChannelPendingBit Clears the NVIC interrupt pending bits. NVIC_GetCurrentActiveHandler Returns the current active Handler (IRQ Channel and SystemHandler) identifier. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnNVICuFirmware library functionsFunction name Description NVIC_GetIRQChannelActiveBitStatus Checks whether the specified IRQ Channel active bit is set or not. NVIC_GetCPUID Returns the ID number, the version number and the implementation details of the Cortex-M3 core. NVIC_SetVectorTable Sets the vector table location and offset. NVIC_GenerateSystemReset Generate a system reset. NVIC_GenerateCoreReset Generate a Core (Core + NVIC) reset. NVIC_SystemLPConfig Selects the condition for the system to enter low power mode. NVIC_SystemHandlerConfig Enables or disables the specified System Handlers. NVIC_SystemHandlerPriorityConfig Configures the specified System Handlers priority. NVIC_GetSystemHandlerPendingBitStatus Checks whether the specified System handlers pending bit is set or not. NVIC_SetSystemHandlerPendingBit Sets System Handler pending bit. NVIC_ClearSystemHandlerPendingBit Clears System Handler pending bit. NVIC_GetSystemHandlerActiveBitStatus Checks whether the specified System handlers active bit is set or not. NVIC_GetFaultHandlerSources Returns the system fault handlers sources. NVIC_GetFaultAddress Returns the address of the location that generated a fault handler. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIu外部中断的外部中断的SFR首地址：首地址：0x4001 0400Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIu外部中断的外部中断的SFR首地址：首地址：0x4001 0400Register Description IMR Interrupt Mask Register EMR Event Mask Register RTSR Rising Trigger Selection Register FTSR Falling Trigger Selection Register SWIR Software Interrupt Event Register PR Pending Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIuThe EXTI_TypeDef is in stm32f10x_map.htypedef structvu32 IMR;vu32 EMR;vu32 RTSR;vu32 FTSR;vu32 SWIER;vu32 PR; EXTI_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIuThe EXTI_TypeDef is in stm32f10x_map.h.#define PERIPH_BASE (u32)0x40000000)#define APB1PERIPH_BASE PERIPH_BASE#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000).#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)#ifndef DEBUG.#ifdef _EXTI#define EXTI (EXTI_TypeDef *) EXTI_BASE)#endif /*_EXTI */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIuThe EXTI_TypeDef is in stm32f10x_map.h.#else /* DEBUG */.#ifdef _EXTIEXT EXTI_TypeDef *EXTI;#endif /*_EXTI */.#endifWhen using the Debug mode, EXTI pointer is initialized in stm32f10x_lib.c file:#ifdef _EXTIEXTI = (EXTI_TypeDef *) EXTI_BASE;#endif /*_EXTI */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnEXTIuFirmware library functionsFunction name Description EXTI_DeInit Resets the EXTI peripheral registers to their default reset values. EXTI_Init Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct. EXTI_StructInit Fills each EXTI_InitStruct member with its default value. EXTI_GenerateSWInterrupt Generates a software interrupt. EXTI_GetFlagStatus Checks whether the specified EXTI line flag is set or not. EXTI_ClearFlag Clears the EXTIs line pending flags. EXTI_GetITStatus Checks whether the specified EXTI line is asserted or not. EXTI_ClearITPendingBit Clears the EXTIs line pending bits. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuSFR Mapu地址：地址： 0x4000 7000 - 0x4000 73FFRegister Description CR Power Control Register CSR Power Control Status Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuPWR_TypeDef is in stm32f10x_map.htypedef structvu32 CR;vu32 CSR; PWR_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuPeripheral is in stm32f10x_map.h:#define PERIPH_BASE (u32)0x40000000)#define APB1PERIPH_BASE PERIPH_BASE#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)#define PWR_BASE (APB1PERIPH_BASE + 0x7000)#ifndef DEBUG.#ifdef _PWR#define PWR (PWR_TypeDef *) PWR_BASE)#endif /*_PWR */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuPeripheral is in stm32f10x_map.h:.#else /* DEBUG */.#ifdef _PWREXT PWR_TypeDef *PWR;#endif /*_PWR */.#endifEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuPeripheral is in stm32f10x_map.h:lWhen using the Debug mode, PWR pointer is initialized in stm32f10x_lib.c file:#ifdef _PWRPWR = (PWR_TypeDef *) PWR_BASE;#endif /*_PWR */To access the PWR registers, _PWR must be defined in stm32f10x_conf.h as follows:#define _PWREmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnPWRuFirmware library functionsFunction name Description PWR_DeInit Resets the PWR peripheral registers to their default reset values. PWR_BackupAccessCmd Enables or disables access to the RTC and backup registers. PWR_PVDCmd Enables or disables the Power Voltage Detector(PVD). PWR_PVDLevelConfig Configures the voltage threshold detected by the Power Voltage Detector(PVD). PWR_WakeUpPinCmd Enables or disables the WakeUp Pin functionality. PWR_EnterSTOPMode Enters Stop mode. PWR_EnterSTANDBYMode Enters Standby mode. PWR_GetFlagStatus Checks whether the specified PWR flag is set or not. PWR_ClearFlag Clears the PWRs pending flags. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register DescriptionlFLASH registersl地址：地址：0x4002 2000 - 0x4002 23FFRegister Description ACR Flash Access Control Register KEYR FPEC Key Register OPTKEYR Option Byte Key Register SR Flash Status Register CR Flash Control Register AR Flash Address Register OBR Option Byte and Status Register WRPR Option Byte write protection Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register DescriptionlOption Bytes registers (OB)l地址：地址：0x1FFFF800Register Description RDP Read Out Option Byte USER User Option Byte Data0 Data0 Option Byte Data1 Data1 Option Byte WRP0 Write Protection 0 Option Byte WRP1 Write Protection 1 Option Byte WRP2 Write Protection 2 Option Byte WRP3 Write Protection 3 Option Byte Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register structureslFLASH_TypeDef in stm32f10x_map.h:typedef structvu32 ACR;vu32 KEYR;vu32 OPTKEYR;vu32 SR;vu32 CR;vu32 AR;vu32 RESERVED;vu32 OBR;vu32 WRPR; FLASH_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register structureslOB_TypeDef in stm32f10x_map.h:typedef structvu16 RDP;vu16 USER;vu16 Data0;vu16 Data1;vu16 WRP0;vu16 WRP1;vu16 WRP2;vu16 WRP3; OB_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register structureslPeripheral is in stm32f10x_map.h:/* Flash registers base address */#define FLASH_BASE (u32)0x40022000)/* Flash Option Bytes base address */#define OB_BASE (u32)0x1FFFF800)#ifndef DEBUG.#ifdef _FLASH#define FLASH (FLASH_TypeDef *) FLASH_BASE)#define OB (OB_TypeDef *) OB_BASE)#endif /*_FLASH */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register structureslPeripheral is in stm32f10x_map.h:.#else /* DEBUG */.#ifdef _FLASHEXT FLASH_TypeDef *FLASH;EXT OB_TypeDef *OB;#endif /*_FLASH */.#endifEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFLASH register structureslPeripheral is in stm32f10x_map.h:Debug mode, in stm32f10x_lib.c:#ifdef _FLASHFLASH = (FLASH_TypeDef *) FLASH_BASE;OB = (OB_TypeDef *) OB_BASE;#endif /*_FLASH */To access the FLASH registers, _FLASH must be defined in stm32f10x_conf.h as follows:#define _FLASHBy default only the functions performing FLASH configuration (latency, prefetch, half cycle) are enabled.To enable FLASH program/erase/protections functions, _FLASH_PROG must be defined in stm32f10x_conf.h as follows: #define _FLASH_PROGEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFirmware library functionslFLASH library functionFunction name Description FLASH_SetLatency Sets the code latency value. FLASH_HalfCycleAccessCmd Enables or disables the Half cycle FLASH access. FLASH_PrefetchBufferCmd Enables or disables the Prefetch Buffer. FLASH_Unlock Unlocks the FLASH Program Erase Controller. FLASH_Lock Locks the Flash Program Erase Controller. FLASH_ErasePage Erases a specified FLASH page. FLASH_EraseAllPages Erases all FLASH pages. FLASH_EraseOptionBytes Erases the FLASH option bytes. FLASH_ProgramWord Programs a word at a specified address. FLASH_ProgramHalfWord Programs a half word at a specified address. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFirmware library functionslFLASH library functionFunction name Description FLASH_ProgramOptionByteData Programs a half word at a specified Option Byte Data address. FLASH_EnableWriteProtection Write protects the desired pages FLASH_ReadOutProtection Enables or disables the read out protection. FLASH_UserOptionByteConfig Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. FLASH_GetUserOptionByte Returns the FLASH User Option Bytes values. FLASH_GetWriteProtectionOptionByte Returns the FLASH Write Protection Option Bytes Register value. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnFLASHuFirmware library functionslFLASH library functionFunction name Description FLASH_GetReadOutProtectionStatus Checks whether the FLASH Read Out Protection Status is set or not. FLASH_GetPrefetchBufferStatus Checks whether the FLASH Prefetch Buffer status is set or not. FLASH_ITConfig Enables or disables the specified FLASH interrupts. FLASH_GetFlagStatus Checks whether the specified FLASH flag is set or not. FLASH_ClearFlag Clears the FLASH pending flags. FLASH_GetStatus Returns the FLASH Status. FLASH_WaitForLastOperation Waits for a Flash operation to complete or a TIMEOUT to occur. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSysTickuSysTick register Descriptionl地址：地址：0xE000E000Name of registerTypeAddressReset valueSysTick Control and Status RegisterRead/write0xE000E010 0x00000000SysTick Reload Value RegisterRead/write0xE000E014 UnpredictableSysTick Current Value RegisterRead/write clear 0xE000E018 UnpredictableSysTick Calibration Value RegisterRead-only0xE000E01C STCALIBRegister Description CTRL SysTick Control and Status Register LOAD SysTick Reload value Register VAL SysTick Current value Register CALIB SysTick Calibration value Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSysTickuSysTick register structureslFLASH_TypeDef in stm32f10x_map.h:typedef structvu32 CTRL;vu32 LOAD;vu32 VAL;vuc32 CALIB; SysTick_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSysTickuSysTick register structureslPeripheral is in stm32f10x_map.h:#define SCS_BASE (u32)0xE000E000)#define SysTick_BASE (SCS_BASE + 0x0010)#ifndef DEBUG.#ifdef _SysTick#define SysTick (SysTick_TypeDef *) SysTick_BASE)#endif /*_SysTick */.#else /* DEBUG */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSysTickuSysTick register structureslPeripheral is in stm32f10x_map.h:#ifdef _SysTickEXT SysTick_TypeDef *SysTick;#endif /*_SysTick */.#endifDebug mode in stm32f10x_lib.c:#ifdef _SysTickSysTick = (SysTick_TypeDef *) SysTick_BASE;#endif /*_SysTick */To access the SysTick registers, _SysTick must be defined in stm32f10x_conf.h as follows:#define _SysTickEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSysTickuFirmware library functionsFunction name Description SysTick_CLKSourceConfig Configures the SysTick clock source. SysTick_SetReload Sets SysTick Reload value. SysTick_CounterCmd Enables or disables the SysTick counter. SysTick_ITConfig Enables or disables the SysTick Interrupt. SysTick_GetCounter Gets SysTick counter value. SysTick_GetFlagStatus Checks whether the specified SysTick flag is set or not. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register Descriptionl地址：地址：0x4001 3800 - 0x4001 3BFFl地址：地址：0x4000 4400 - 0x4000 47FFRegister Description SR USART Status Register DR USART Data Register BRR USART BaudRate Register CR1 USART Control Register 1 CR2 USART Control Register 2 CR3 USART Control Register 3 GTPR USART Guard-Time and Prescaler Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register DescriptionEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslUSART in stm32f10x_map.h:typedef structvu16 SR;u16 RESERVED1;vu16 DR;u16 RESERVED2;vu16 BRR;u16 RESERVED3;vu16 CR1;u16 RESERVED4;vu16 CR2;u16 RESERVED5;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslUSART_TypeDef in stm32f10x_map.h:typedef structvu16 CR3;u16 RESERVED6;vu16 GTPR;u16 RESERVED7; USART_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslPeripheral in stm32f10x_map.h:.#define PERIPH_BASE (u32)0x40000000)#define APB1PERIPH_BASE PERIPH_BASE#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)#define USART1_BASE (APB2PERIPH_BASE + 0x3800)#define USART2_BASE (APB1PERIPH_BASE + 0x4400)#define USART3_BASE (APB1PERIPH_BASE + 0x4800)#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)#define UART5_BASE (APB1PERIPH_BASE + 0x5000)Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslPeripheral in stm32f10x_map.h:#ifndef DEBUG.#ifdef _USART1#define USART1 (USART_TypeDef *) USART1_BASE)#endif /*_USART1 */#ifdef _USART2#define USART2 (USART_TypeDef *) USART2_BASE)#endif /*_USART2 */#ifdef _USART3#define USART3 (USART_TypeDef *) USART3_BASE)#endif /*_USART3 */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslPeripheral in stm32f10x_map.h:#ifdef _UART4#define UART4 (USART_TypeDef *) UART4_BASE)#endif /*_UART4 */#ifdef _UART5#define UART5 (USART_TypeDef *) UART5_BASE)#endif /*_UART5 */.#else /* DEBUG */.#ifdef _USART1EXT USART_TypeDef *USART1;#endif /*_USART1 */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslPeripheral in stm32f10x_map.h:#ifdef _USART2EXT USART_TypeDef *USART2;#endif /*_USART2 */#ifdef _USART3EXT USART_TypeDef *USART3;#endif /*_USART3 */#ifdef _UART4EXT USART_TypeDef *UART4;#endif /*_UART4 */#ifdef _UART5EXT USART_TypeDef *UART5;#endif /*_UART5 */.#endifEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslDebug mode in the stm32f10x_lib.c:.#ifdef _USART1USART1 = (USART_TypeDef *) USART1_BASE;#endif /*_USART1 */#ifdef _USART2USART2 = (USART_TypeDef *) USART2_BASE;#endif /*_USART2 */#ifdef _USART3USART3 = (USART_TypeDef *) USART3_BASE;#endif /*_USART3 */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslDebug mode in the stm32f10x_lib.c:#ifdef _UART4UART4 = (USART_TypeDef *) UART4_BASE;#endif /*_USART4 */#ifdef _UART5UART5 = (USART_TypeDef *) UART5_BASE;#endif /*_UART5 */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART register structureslDebug mode in the stm32f10x_lib.c:Defined in stm32f10x_conf.h:.#define _USART#define _USART1#define _USART2#define _USART3#define _UART4#define _UART5Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART library functionsFunction name Description USART_DeInit Resets the USARTx peripheral registers to their default reset values. USART_Init Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct. USART_StructInit Fills each USART_InitStruct member with its default value. USART_ClockInit Initializes the USARTx peripheral clock according to the specified parameters in the USART_ClockInitStruct. USART_ClockStructInit Fills each USART_ClockInitStruct member with its default value. USART_Cmd Enables or disables the specified USART peripheral. USART_ITConfig Enables or disables the specified USART interrupts. USART_DMACmd Enables or disables the USART DMA interface. USART_SetAddress Sets the address of the USART node. USART_WakeUpConfig Selects the USART WakeUp method. USART_ReceiverWakeUpCmd Determines if the USART is in mute mode or not. USART_LINBreakDetectionConfig Sets the USART LIN Break detection length. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnUSARTuUSART library functionsFunction name Description USART_LINCmd Enables or disables the USARTx LIN mode. USART_SendData Transmits single data through the USARTx peripheral. USART_ReceiveData Returns the most recent received data by the USARTx peripheral. USART_SendBreak Transmits break characters. USART_SetGuardTime Sets the specified USART guard time. USART_SetPrescaler Sets the USART clock prescaler. USART_SmartCardCmd Enables or disables the USART Smart Card mode. USART_SmartCardNackCmd Enables or disables NACK transmission. USART_HalfDuplexCmd Enables or disables the USART Half Duplex mode. USART_IrDAConfig Configures the USART IrDA mode. USART_IrDACmd Enables or disables the USART IrDA mode. USART_GetFlagStatus Checks whether the specified USART flag is set or not. USART_ClearFlag Clears the USARTx pending flags. USART_GetITStatus Checks whether the specified USART interrupt has occurred or not. USART_ClearITPendingBit Clears the USARTx interrupt pending bits. Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register DescriptionlGPIO地址：地址：0x4001 0800 - 0x4001 23FFlAFIO地址：地址：0x4001 0000 - 0x4001 03FFlSFRRegister Description CRL Port Control Register low CRH Port Control Register High IDR Input Data Register ODR Output Data Register BSRR Bit Set Reset Register BRR Bit Reset Register LCKR Lock Register EVCR Event Control Register MAPR Remap Debug and AF Register EXTICR EXTI Line 0 to Line 15 Configuration Register Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register DescriptionEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register DescriptionEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register DescriptionEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslGPIO_TypeDef in stm32f10x_map.h:typedef structvu32 CRL;vu32 CRH;vu32 IDR;vu32 ODR;vu32 BSRR;vu32 BRR;vu32 LCKR; GPIO_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslAFIO_TypeDef in stm32f10x_map.h:typedef structvu32 EVCR;vu32 MAPR;vu32 EXTICR4; AFIO_TypeDef;Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslPeripheral in stm32f10x_map.h:#define PERIPH_BASE (u32)0x40000000)#define APB1PERIPH_BASE PERIPH_BASE#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslPeripheral in stm32f10x_map.h:#ifndef DEBUG#ifdef _AFIO#define AFIO (AFIO_TypeDef *) AFIO_BASE)#endif /*_AFIO */#ifdef _GPIOA#define GPIOA (GPIO_TypeDef *) GPIOA_BASE)#endif /*_GPIOA */#ifdef _GPIOB#define GPIOB (GPIO_TypeDef *) GPIOB_BASE)#endif /*_GPIOB */#ifdef _GPIOC#define GPIOC (GPIO_TypeDef *) GPIOC_BASE)#endif /*_GPIOC */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslPeripheral in stm32f10x_map.h:#ifdef _GPIOD#define GPIOD (GPIO_TypeDef *) GPIOD_BASE)#endif /*_GPIOD */#ifdef _GPIOE#define GPIOE (GPIO_TypeDef *) GPIOE_BASE)#endif /*_GPIOE */#ifdef _GPIOF#define GPIOF (GPIO_TypeDef *) GPIOF_BASE)#endif /*_GPIOF */#ifdef _GPIOG#define GPIOG (GPIO_TypeDef *) GPIOG_BASE)#endif /*_GPIOG */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslPeripheral in stm32f10x_map.h:#else /* DEBUG */#ifdef _AFIOEXT AFIO_TypeDef *AFIO;#endif /*_AFIO */#ifdef _GPIOAEXT GPIO_TypeDef *GPIOA;#endif /*_GPIOA */#ifdef _GPIOBEXT GPIO_TypeDef *GPIOB;#endif /*_GPIOB */#ifdef _GPIOCEXT GPIO_TypeDef *GPIOC;#endif /*_GPIOC */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslPeripheral in stm32f10x_map.h:#ifdef _GPIODEXT GPIO_TypeDef *GPIOD;#endif /*_GPIOD */#ifdef _GPIOEEXT GPIO_TypeDef *GPIOE;#endif /*_GPIOE */#ifdef _GPIOFEXT GPIO_TypeDef *GPIOF;#endif /*_GPIOF */#ifdef _GPIOGEXT GPIO_TypeDef *GPIOG;#endif /*_GPIOG */#endifEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslDebug mode in the stm32f10x_lib.c:#ifdef _GPIOAGPIOA = (GPIO_TypeDef *) GPIOA_BASE;#endif /*_GPIOA */#ifdef _GPIOBGPIOB = (GPIO_TypeDef *) GPIOB_BASE;#endif /*_GPIOB */#ifdef _GPIOCGPIOC = (GPIO_TypeDef *) GPIOC_BASE;#endif /*_GPIOC */#ifdef _GPIODGPIOD = (GPIO_TypeDef *) GPIOD_BASE;#endif /*_GPIOD */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslDebug mode in the stm32f10x_lib.c:#ifdef _GPIOEGPIOE = (GPIO_TypeDef *) GPIOE_BASE;#endif /*_GPIOE */#ifdef _GPIOFGPIOF = (GPIO_TypeDef *) GPIOG_BASE;#endif /*_GPIOF */#ifdef _GPIOGGPIOG = (GPIO_TypeDef *) GPIOG_BASE;#endif /*_GPIOG */#ifdef _AFIOAFIO = (AFIO_TypeDef *) AFIO_BASE;#endif /*_AFIO */Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO register structureslDebug mode Defined in stm32f10x_conf.h:#define _GPIO#define _GPIOA#define _GPIOB#define _GPIOC#define _GPIOD#define _GPIOE#define _GPIOF#define _GPIOG#define _AFIOEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO library functionsFunction name Description GPIO_DeInit Resets the GPIOx peripheral registers to their default reset values. GPIO_AFIODeInit Resets the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values. GPIO_Init Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. GPIO_StructInit Fills each GPIO_InitStruct member with its default value. GPIO_ReadInputDataBit Reads the specified input port pin GPIO_ReadInputData Reads the specified GPIO input data port GPIO_ReadOutputDataBit Reads the specified output data port bit GPIO_ReadOutputData Reads the specified GPIO output data port Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnGPIOuGPIO重映射实例重映射实例Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSFR_NameuSFR_Name register Descriptionl地址：地址：Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSFR_NameuSFR_Name register structureslSFR_Name_TypeDef in stm32f10x_map.h:lPeripheral in stm32f10x_map.h:lDebug mode in the stm32f10x_lib.c:lDebug mode Defined in stm32f10x_conf.h:Embedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnSFR_NameuSFR_Name library functionsEmbedded System Interface Design and Application信息信息学院学院STM32F103的的SFRnOthersuDMA、PWR、ustm32f10x_map.huSTM32F10xxx_Register_EN_1.pdfEmbedded System Interface Design and Application信息信息学院学院STM32F103的应用的应用n供供电电方案方案 素材和资料部分来自素材和资料部分来自网络，如有帮助请下载网络，如有帮助请下载!