www.eefocus.comVerilog基础硬核实战营培训关于Verilog及设计流程Veriog代码结构-模块、端口、注释常数、运算符芯片设计流程SpecificationBehavioraldescriptionRTLdescriptionFunctionalverification&testGatelevelnetlistLogicsynthesisLogicverificationandtestingFloorplanning,autoplace&routePhysicallayoutLayoutverificationImplementation自上而下的层次化结构设计顶层模块子模块1子模块2基本模块3基本模块2基本模块1不同的设计方式列出了一系列元件以及它们之间如何连接纯结构化就如原理图，但是用文字来描述Proceduralcode,类似C编程描述一个元件的功能以及如何实现该功能很少的结构化细节(除了模块之间的互联)SpecifiestransferofdatabetweenregistersSomestructuralinformationisavailable(RTL)Sometimessimilartobehavior模块接口:端口和参数声明主体部分:模块的内部部分附加部分(可选加)模块的名字标注：一行标注(/.)一块标注(/*.*/)模块的描述(推荐的选项)fin1in2inNout1out2outMmy_modulemodule my_module(out1, ., inN);output out1, ., outM;input in1, ., inN;. / declarations. / description of f (maybe. / sequential)endmodule对应于电路中的一个元件可以跟其它元件连接，并被多次引用I/O端口在模块的顶部列出，被声明为Input、Output、或Inout（用于三态的总线中）端口声明意味着变量都是Wires关键词所有关键词都是用小写字母来定义例如:module,endmoduleinput,output,inoutreg,integer,real,timenot,and,nand,or,nor,xorparameterbegin,endfork,joinspecify,hmoduleVerilog设计中的基础块，用于构建设计中的层次化endmodule结束一个模块，不是一个语句ModuleDeclarationmodulemodule_name(module_port, module_port,);Example:modulefull_adder(A,B,c_in,c_out,S);输入定义：向量inputlist of input identifiers;例如:inputA,B,c_in;矢量input范围list of input identifiers;例如:input15:0A,B,data;输出定义：向量举例:outputc_out,OV,MINUS;矢量举例:output7:0ACC,REG_IN,data_out;Nets:硬件单元之间的物理连接-用关键词“wire”定义不保留他们的值，它们的数值来自一个门或其它模块的驱动不能通过一个initial或always块进行赋值Registers: 类似计算机里的存储器在通过一个initial或always块赋值之前一直保留其数值可以用来模型化锁存器、寄存器等，但不是完全对应变量：wire/reg8hax=1010xxxx12o3zx7=011zzzxxx11112h046-12位长的16进制数Verilog的数值是没有符号的：例如：C4:0 = A3:0 + B3:0;ifA=0110(6)andB=1010(-6)C=10000not0000i.e.,Biszero-padded,notsign-extendedVerilog的数字表示位数2进制 b或B8进制 o或O10进制 dorD16进制 horH连续的字符0-f,x,z变量的多种形式Wires和registers可以是位、向量以及数组wirea;/一个简单的wiretri15:0dbus;/16-bit三态总线try#(5,4,8)b;/带延迟的Wirereg-1:4vec;/6-bit的register（寄存器）triage(small)q;/Wirestoresasmallchargeintegerimem0:1023;/1024整数的数组reg31:0dcache0:63;/一个32-bit的存储器数据值四种数据的值数据表示类型：二进制：6b100101十六进制：6h250:零,逻辑低电平，错误,接地1:一,逻辑高电平,电源X:状态未知Z:高阻、三态、未连接,无驱动多位数的向量A3:0 - 4 bits的向量: A3, A2, A1, A0被当成无符号的整数值截断bits/vectors得到一个vectorB7:0 = A3, A3, A3, A3, A3:0;B7:0 = 4A3, A3:0;建议的写法: a7:0 = b7:0 + c;不建议的写法: a = b + c;端口定义寄存输出时延声明和事件控制传输延迟单个延时:and#3G1(y,a,b,c);上升/下降延时and#(3,5)G2(y,a,b)Rise/Fall/Turnoffbuff0#(3,6.5)(y,x_in,en)Rise/Fall/TurnoffwithMin:typ:Maxbuff1#(3:4:5,4:5:6,7:8:9)(y,x_in,en);延时声明-以一个#符号标明-Delaystheexecutionofthestatementimmediatelyafter-Inertialdelaymodel(ignoresglitches)-Additivewithblockingstatements事件控制声明：-Edgesensitive,representedwithasign-DelaystheexecutionuntilexpressiontransitionsEx.always(clock)always(posedgeclock)always(aorb)-Levelsensitive,representedwithwaitstatementEx.alwayswait(enable)#20cnt=cnt+1;Verilog中的运算操作位操作逻辑运算Reduction运算算数运算关系运算移位运算位操作-操作符& 位AND| 位OR 位NOT 位XORor 位XNORa = 4b1010;b = 4b1100;c = a;c = a & b;位操作-举例c = a b;a = 4b1010;b = 2b11;逻辑运算&逻辑与AND|逻辑或OR!逻辑非NOTOperandsevaluatedtoONEbitvalue:0, 1 or xResultisONEbitvalue:0, 1 or xA=1;A&B1&00B=0;A|!B1|11C=x;C|Bx|0x butC&B=0移位及条件执行语句 右移 2;/ d = 0010,c = a 1;/ c = 0100cond_expr ? true_expr : false_exprABYselY = (sel)? A : B;举例-比较器module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (A & B); assign Alarger = (A & B); assign Blarger = (A & B);endmodule / 通过4个1位的比较器构建一个4位的比较器module Compare4(A4, B4, Equal, Alarger, Blarger); input 3:0 A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 cp0(A40, B40, e0, Al0, Bl0); Compare1 cp1(A41, B41, e1, Al1, Bl1); Compare1 cp2(A42, B42, e2, Al2, Bl2); Compare1 cp3(A43, B43, e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 | (Al2 & e3) | (Al1 & e3 & e2) | (Al0 & e3 & e2 & e1); assign Blarger = (Alarger & Equal);endmoduleVerilog持续赋值assign A = X | (Y & Z);assign B3:0 = 4b01XX;assign C15:0 = 16h00ff;assign #3 Cout, S3:0 = A3:0 + B3:0 + Cin;use of arithmetic operatormultiple assignment (concatenation)delay of performing computation, only used by simulator, not synthesisuse of Boolean operators( for bit-wise, ! for logical negation)bits can take on four values(0, 1, X, Z)variables can be n-bits wide(MSB:LSB)alwaysblockalways blockAlways waiting for a change to a trigger signalThen executes the bodymodule and_gate (out, in1, in2); inputin1, in2; output out; regout; always (in1 or in2) begin out = in1 & in2; endendmoduleNotarealregister!AVerilogregisterNeededbecauseofassignmentinalwaysblockSpecifieswhenblockisexecutedI.e.,triggeredbywhichsignalsProcedure that describes the function of a circuitCan contain many statements including if, for, while, caseStatements in the always block are executed sequentially(Continuous assignments = are executed in parallel)Entire block is executed at onceFinal result describes the function of the circuit for current set of inputsintermediate assignments dont matter, only the final resultbegin/end used to group statements未完成触发省去一个输入触发信号一般会导致一个时序电路例如:这个”与”门的输出取决于输入的历史module and_gate (out, in1, in2); inputin1, in2; outputout; regout; always (in1) begin out = in1 & in2; endendmoduleIf/ Simple 4:1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D) if (sel = 2b00) Y = A; else if (sel = 2b01) Y = B; else if (sel = 2b10) Y = C; else if (sel = 2b11) Y = D;endmodule/ Simple 4:1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D) if (sel0 = 0) if (sel1 = 0) Y = A; else Y = B; else if (sel1 = 0) Y = C; else Y = D;endmodule另外一种方式Case-1/ Simple 4-1 muxmodule mux4 (sel, A, B, C, D, Y);input 1:0 sel;/ 2-bit control signalinput A, B, C, D;output Y;reg Y;/ target of assignment always (sel or A or B or C or D) case (sel) 2b00: Y = A; 2b01: Y = B; 2b10: Y = C; 2b11: Y = D; endcaseendmodule顺序执行只有第一个匹配的case被执行(implicit break)缺省的case可以用到 Conditions tested intop to bottom orderCase-2/ Simple binary encoder (input is 1-hot)module encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignment always (A) case (A) 8b00000001: Y = 0; 8b00000010: Y = 1; 8b00000100: Y = 2; 8b00001000: Y = 3; 8b00010000: Y = 4; 8b00100000: Y = 5; 8b01000000: Y = 6; 8b10000000: Y = 7; default: Y = 3bXXX;/ Dont care when input is not 1-hot endcaseendmodule/ Priority encodermodule encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignment always (A) case (1b1) A0: Y = 0; A1: Y = 1; A2: Y = 2; A3: Y = 3; A4: Y = 4; A5: Y = 5; A6: Y = 6; A7: Y = 7; default: Y = 3bXXX;/ Dont care when input is all 0s endcaseendmoduleCase-3/ simple encodermodule encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignment always (A) case (1b1)/ synthesis parallel-case A0: Y = 0; A1: Y = 1; A2: Y = 2; A3: Y = 3; A4: Y = 4; A5: Y = 5; A6: Y = 6; A7: Y = 7; default: Y = 3bX;/ Dont care when input is all 0s endcaseendmoduleLike case, but cases can include XX bits not used when evaluating the casesIn other words, you dont care about those bits!/ Priority encodermodule encode (A, valid, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputoutput valid;/ Asserted when an input is not all 0sreg 2:0 Y;/ target of assignmentreg valid; always (A) begin valid = 1; casex (A) 8bXXXXXXX1: Y = 0; 8bXXXXXX10: Y = 1; 8bXXXXX100: Y = 2; 8bXXXX1000: Y = 3; 8bXXX10000: Y = 4; 8bXX100000: Y = 5; 8bX1000000: Y = 6; 8b10000000: Y = 7; default: begin valid = 0; Y = 3bX;/ Dont care when input is all 0s end endcase endendmoduleFor/repeat/forever/ simple encodermodule encode (A, Y);input 7:0 A; / 8-bit input vectoroutput 2:0 Y;/ 3-bit encoded outputreg 2:0 Y;/ target of assignmentinteger i;/ Temporary variables for program onlyreg 7:0 test; always (A) begin test = 8b00000001; Y = 3bX; for (i = 0; i 8; i = i + 1) begin if (A = test) Y = i; test = test 1; end endendmodulewhile (expression) statementExecute statement while expression is truerepeat (expression) statementExecute statement a fixed number of timesforever statementExecute statement forevermodule life (neighbors, self, out); input self; input 7:0 neighbors; output out; reg out; integer count; integer i; always (neighbors or self) begin count = 0; for (i = 0; i8; i = i+1) count = count + neighborsi; out = 0; out = out | (count = 3); out = out | (self = 1) & (count = 2); endendmodule另一个Behavioral的例子always block is executed instantaneously, if there are no delays only the final result is usedintegers are temporary compiler variablesComputing Conways Game of Life ruleCell with no neighbors or 4 neighbors dies; with 2-3 neighbors lives测试设计的电路(CUD)84产生输出到设计的电路中检查设计电路的输出TestbenchStimulusblockTestbench系系统统模型模型激励响应结果检查测试台(testbench)modulemain;rega,b,c;wiresum,carry;fulladderadd(a,b,c,sum,carry);initialbegina=0;b=0;c=0;#5a=0;b=1;c=0;#5a=1;b=0;c=1;#5a=1;b=1;c=1;#5endendmodule测试模块的结构 module ; / / 数据类型声明 / Instantiate module ( / Instantiate module ( 调用被测试的模块) ) / / 施加激励 / / 显示结果endmodulemodulestimulus;regclk;regreset;wire3:0q;/instantiatethedesignblockripple_carry_counterr1(q,clk,reset);/Controltheclockinitialclk=1b0;always#5clk=clk;/Controltheresetinitialbeginreset=1b1;#15reset=1b0;#180reset=1b1;#10reset=1b0;#20$stop;end/Monitortheoutputsinitial$monitor($time,Outputq=%d,q);endmodule测试台产生输入激励信号，也经常包括对数据的观察仿真仿真行为ScheduledusinganeventqueueNon-preemptive,noprioritiesAprocessmustexplicitlyrequestacontextswitchEventsataparticulartimeunorderedSchedulerrunseacheventatthecurrenttime,possiblyschedulingmoreasaresultEvaluationeventscomputefunctionsofinputsUpdateeventschangeoutputsSplitnecessaryfordelays,nonblockingassignments,etc.Evaluationeventreadsvaluesofbandc,addsthem,andschedulesanupdateeventa=b+cUpdateeventwritesnewvalueofaandschedulesanyevaluationeventsthataresensitivetoachangeona两种类型的事件Concurrentprocesses(initial,always)rununtiltheystopatoneofthefollowin#42Scheduleprocesstoresume42timeunitsfromnowwait(cf&of)Resumewhenexpression“cf&of”becomestrue(aorbory)Resumewhena,b,orychanges(posedgeclk)Resumewhenclkchangesfrom0to1仿真InfiniteloopsarepossibleandthesimulatordoesnotcheckforthemThisrunsforever:nocontextswitchallowed,soreadycanneverchangewhile(ready)count=count+1;Instead,usewait(ready);RaceconditionsaboundinVerilogThesecanexecuteineitherorder:finalvalueofaundefined:always(posedgeclk)a=0;always(posedgeclk)a=1;SemanticsofthelanguagecloselytiedtosimulatorimplementationContextswitchingbehaviorconvenientforsimulation,notalwaysbestwaytomodelUndefinedexecutionorderconvenientforimplementingeventqueueVerilog基本单元只是基本的逻辑门andornotbufxornandnorxnorbufif1,bufif0notif1,notif0所有逻辑门的Verilog编码modulegates(a,b,y1,y2,y3,y4,y5,y6,y7);input3:0a,b;output3:0y1,y2,y3,y4,y5,y6,y7;/*7种不同的逻辑门工作于4位的总线上*/assigny1=a;/NOTgateassigny2=a&b;/ANDgateassigny3=a|b;/ORgateassigny4=(a&b);/NANDgateassigny5=(a|b);/NORgateassigny6=ab;/XORgateassigny7=(ab);/XNORgateendmodule示例-加法器module half_adder(S, C, A, B);output S, C;input A, B;wire S, C, A, B;assign S = A B;assign C = A & B;endmoduleHalfAdderABSCABSCHalfAdderha2ABSCHalfAdder1ha1ABSCtin1in2cincoutsumI1I2I3module full_adder(sum, cout, in1, in2, cin);output sum, cout;input in1, in2, cin;wire sum, cout, in1, in2, cin;wire I1, I2, I3;half_adder ha1(I1, I2, in1, in2);half_adder ha2(sum, I3, I1, cin);assign cout = I2 | I3;endmoduleInstancenameModulename举例:全加器module full_adder(sum, cout, in1, in2, cin);output sum, cout;input in1, in2, cin;wire sum, cout, in1, in2, cin;wire I1, I2, I3;half_adder ha1(I1, I2, in1, in2);half_adder ha2(sum, I3, I1, cin);assign cout = I2 | I3;endmoduleInstancenameModulenameHalfAdderha2ABSCHalfAdder1ha1ABSCin1in2cincoutsumI1I2I3赋值Continuousassignmentsassignvaluestonets(vectorandscalar)Theyaretriggeredwheneversimulationcausesthevalueoftheright-handsidetochangeKeyword“assign”e.g.assignout=in1&in2;Proceduralassignmentsdrivevaluesontoregisters(vectorandscalar)TheyOccurwithinproceduressuchasalways andinitialTheyaretriggeredwhentheflowofexecutionreachesthem(likeinC)BlockingandNon-BlockingproceduralassignmentsProceduralAssignmentsBlockingassignmentstatement(=operator)actsmuchlikeintraditionalprogramminglanguages.ThewholestatementisdonebeforecontrolpassesontothenextstatementNonblockingassignmentstatement(=operator)evaluatesalltheright-handsidesforthecurrenttimeunitandassignstheleft-handsidesattheendofthetimeunit基于延时的定时控制DelayControl(#)Expressionspecifiesthetimedurationbetweeninitiallyencounteringthestatementandwhenthestatementactuallyexecutes.DelayinProceduralAssignmentsInter-StatementDelayIntra-StatementDelayForexample:Inter-StatementDelay#10A=A+1;Intra-StatementDelayA=#10A+1;时序表述：if/casemodule decoder(o,enb_,sel) ;output 7:0 o ;input enb_ ;input 2:0 sel ;reg 7:0 o ;always (enb_ or sel) if(enb_)o = 8b1111_1111 ; elsecase(sel)3b000 : o = 8b1111_1110 ;3b001 : o = 8b1111_1101 ;3b010 : o = 8b1111_1011 ;3b011 : o = 8b1111_0111 ;3b100 : o = 8b1110_1111 ;3b101 : o = 8b1101_1111 ;3b110 : o = 8b1011_1111 ;3b111 : o = 8b0111_1111 ;default : o = 8bx ;endcase endmoduleif(expr1)true_stmt1;elseif(expr2)true_stmt2;.elsedef_stmt;E.g.4-to-1mux:module mux4_1(out, in, sel);output out;input 3:0 in;input 1:0 sel;reg out;wire 3:0 in;wire 1:0 sel;always (in or sel)if (sel = 0)out = in0;else if (sel = 1)out = in1;else if (sel = 2)out = in2;else out = in3;endmodulecase(expr)item_1,.,item_n:stmt1;item_n+1,.,item_m:stmt2;.default:def_stmt;endcaseE.g.4-to-1mux:module mux4_1(out, in, sel);output out;input 3:0 in;input 1:0 sel;reg out;wire 3:0 in;wire 1:0 sel;always (in or sel)case (sel)0: out = in0;1: out = in1;2: out = in2;3: out = in3;endcaseendmodule带使能控制的3-to8译码矢量NetsandRegisterscanbedeclaredasvectorsIfnobitwidthisspecified,1bitisassumedwire7:0a;reg0:31addr1,addr2;Subsetsofbitscanbeselectedaddr12:0=addr23:1;其它数据类型Verilogallowsintegers,real,andtimetypesArrayscanbemadefromothertypes-Arrayscanbemultidimensional-Avectorisconceptuallyasingleelementswithmanybits-Anarrayismanyelementsputtogetherwire7:0x;/avectorwirex7:0;/anarraywire7:0x7:0;/anarrayofvectorswirex7:07:0;/atwodimensionalarrayParametersareconstantsparameterline_width=80;DataflowDescriptions,ContinuousAssignmentsassignout=i1&i2;Usetheassignkeyword(inmostcases)Lefthandsidemustbeanetofsomekind(scalarorvector),notaregisterRighthandsidecanberegisters,nets,orfunctioncallsContinuousassignmentsarealwaysactive.ExecutionhardtotraceTheyareevaluatedwheneverarighthandsideoperandchangesvalueDelays(inertial)canbeaddedtorepresentcomponentdelaysassign#10out=i1&i2;Continuousassignmentcanbeimplicitinanetdeclarationwireout=i1&i2;module edge_dff(q, qbar, d, clk, clear);/ Inputs and outputsoutput q,qbar;input d, clk, clear;/ Internal variableswire s, sbar, r, rbar,cbar;/Make complement of clearassign cbar = clear;/ Input latchesassign sbar = (rbar & s),s = (sbar & cbar & clk),r = (rbar & clk & s),rbar = (r & cbar & d);/ Output latchassign q = (s & qbar),qbar = (q & r & cbar);endmoduleBehavioralModeling,StructuredProceduresInitialblocks-Theblockexecutesonlyonce-Bydefault,startsattime0(butthiscanbechanged)-OftenusedforinitializationAlwaysblocksandinitialblocks-Parallelconstructs:allblockscanexecuteinparallelmodule stimulus;reg x,y, a,b, m;initialbegin#5 a = 1b1; #25 b = 1b0;endinitialbegin#10 x = 1b0;#25 y = 1b1;endendmoduleAlwaysblocks-Theblockexecutesinaninfiniteloop-Bydefault,startsattime0(butthiscanbechanged)-Representsaconcurrenthardwareblock-Needsadelaymodule clock_gen; reg clock;initial clock = 1b0;always #10 clock = clock;initial #1000 $finish;endmoduleinitialbeginimperativestatementsendRunswhensimulationstartsTerminateswhencontrolreachestheendGoodforprovidingstimulusalwaysbeginimperativestatementsendRunswhensimulationstartsRestartswhencontrolreachestheendGoodformodeling/specifyinghardwareRununtiltheyencounteradelayinitialbegin#10a=1;b=0;#10a=0;b=1;endorawaitforaneventalways(posedgeclk)q=d;alwaysbeginwait(i);a=0;wait(i);a=1;endInitialandAlwaysProceduralStatementsVeriloghastwotypesofproceduralassignmentFundamentalproblem:Inasynchronoussystem,allflip-flopssamplesimultaneouslyInVerilog,always(posedgeclk)blocksruninsomeundefinedsequenceBlockingAssignments-Representedwitha=sign-Allblockingassignmentsareexecutedinsequencemodule dummy;reg x, y, z;reg 15:0 reg_a, reg_b;integer count;initialbegin x = 0; y = 1; z = 1; count = 0; reg_a = 16b0; reg_b = reg_a; reg_a2 = #15 1; reg_b15:13 = #10 x, y, z; count = count + 1;endNon-BlockingAssignments-Representedwitha=sign-Allnon-blockingassignmentsareexecutedinparallel-Trynottomixwithblockingassignmentsmodule dummy;reg x, y, z;reg 15:0 reg_a, reg_b;integer count;initialbegin x = 0; y = 1; z = 1; count = 0; reg_a = 16b0; reg_b = reg_a; reg_a2 = #15 1; reg_b15:13 = #10 x, y, z; count = count + 1;end时序电路设计afeedbackpaththestateofthesequentialcircuitsthestatetransitionsynchronouscircuitsasynchronouscircuitsExamples-DlatchDflip-flopregisterMemoryelementsCombinationalcircuitInputsOutputsTwoMainComponentsofVerilogConcurrent,event-triggeredprocesses(behavioral)InitialandAlwaysblocksImperativecodethatcanperformstandarddatamanipulationtasks(assignment,if-then,case)ProcessesrununtiltheydelayforaperiodoftimeorwaitforatriggeringeventStructure(Plumbing)VerilogprogrambuildfrommoduleswithI/OinterfacesModulesmaycontaininstancesofothermodulesModulescontainlocalsignals,etc.ModuleconfigurationisstaticandallrunconcurrentlyCopyright2001StephenA.EdwardsAllrightsreservedMultiplexerBuiltWithAlwaysmodulemux(f,a,b,sel);outputf;inputa,b,sel;regf;always(aorborsel)if(sel)f=a;elsef=b;endmoduleabselfModulesmaycontainoneormorealwaysblocksSensitivitylistcontainssignalswhosechangetriggerstheexecutionoftheblockCopyright2001StephenA.EdwardsAllrightsreservedMultiplexerBuiltWithAlwaysmodulemux(f,a,b,sel);outputf;inputa,b,sel;regf;always(aorborsel)if(sel)f=a;elsef=b;endmoduleabselfAregbehaveslikememory:holdsitsvalueuntilimperativelyassignedotherwiseBodyofanalwaysblockcontainstraditionalimperativecodeCopyright2001StephenA.EdwardsAllrightsreservedMuxwithContinuousAssignmentmodulemux(f,a,b,sel);outputf;inputa,b,sel;assignf=sel?a:b;endmoduleabselfLHSisalwayssettothevalueontheRHSAnychangeontherightcausesreevaluationCopyright2001StephenA.EdwardsAllrightsreservedMuxwithUser-DefinedPrimitiveprimitivemux(f,a,b,sel);outputf;inputa,b,sel;table1?0:1;0?0:0;?11:1;?01:0;11?:1;00?:0;endtableendprimitiveabselfBehaviordefinedusingatruthtablethatincludes“dontcares”Thisisalesspessimisticthanothers:whena&bmatch,selisignored(othersproduceX)Copyright2001StephenA.EdwardsAllrightsreservedStructuralModelingCopyright2001StephenA.EdwardsAllrightsreservedModulesandInstancesBasicstructureofaVerilogmodule:modulemymod(output1,output2,input1,input2);outputoutput1;output3:0output2;inputinput1;input2:0input2;endmoduleVerilogconventionlistsoutputsfirstCopyright2001StephenA.EdwardsAllrightsreservedInstantiatingaModuleInstancesofmodulemymod(y,a,b);looklikemymodmm1(y1,a1,b1);/Connect-by-positionmymod(y2,a1,b1),(y3,a2,b2);/Instancenamesomittedmymodmm2(.a(a2),.b(b2),.y(c2);/Connect-by-nameCopyright2001StephenA.EdwardsAllrightsreservedASequentialPrimitivePrimitivedff(q,clk,data);outputq;regq;inputclk,data;table/clkdataqnew-q(01)0:?:0;/Latcha0(01)1:?:1;/Latcha1(0x)1:1:1;/Holdwhendandqboth1(0x)0:0:0;/Holdwhendandqboth0(?0)?:?:-;/Holdwhenclkfalls?(?):?:-;/HoldwhenclkstableendtableendprimitiveCopyright2001StephenA.EdwardsAllrightsreservedContinuousAssignmentAnotherwaytodescribecombinationalfunctionConvenientforlogicalordatapathspecificationswire8:0sum;wire7:0a,b;wirecarryin;assignsum=a+b+carryin;DefinebuswidthsContinuousassignment:permanentlysetsthevalueofsumtobea+b+carryinRecomputedwhena,b,orcarryinchangesCopyright2001StephenA.EdwardsAllrightsreservedImperativeStatementsif(select=1)y=a;elsey=b;case(op)2b00:y=a+b;2b01:y=ab;2b10:y=ab;default:y=hxxxx;endcaseLoopsAincreasingsequenceofvaluesonanoutputreg3:0i,output;for(i=0;i=15;i=i+1)beginoutput=i;#10;endForLoopsWhileLoopsAincreasingsequenceofvaluesonanoutputreg3:0i,output;i=0;while(I=15)beginoutput=i;#10i=i+1;endmoduleDiv20x(rst,clk,cet,cep,count,tc);/TITLEDivide-by-20Counterwithenables/enableCEPisaclockenableonly/enableCETisaclockenableand/enablestheTCoutput/acounterusingtheVeriloglanguageparametersize=5;parameterlength=20;inputrst;/Theseinputs/outputsrepresentinputclk;/connectionstothemodule.inputcet;inputcep;outputsize-1:0count;outputtc;regsize-1:0count;/Signalsassigned/withinanalways/(orinitial)block/mustbeoftyperegwiretc;/Othersignalsareoftypewire/Thealwaysstatementbelowisaparallel/executionstatementthat/executesanytimethesignals/rstorclktransitionfromlowtohighalways(posedgeclkorposedgerst)if(rst)/Thiscausesresetofthecntrcount=size1b0;elseif(cet&cep)/Enablesbothtruebeginif(count=length-1)count=size1b0;elsecount=count+1b1;end/thevalueoftciscontinuouslyassigned/thevalueoftheexpressionassigntc=(cet&(count=length-1);endmodule计数器举例.rega,b,c,d;wiree;.always(bore)begina=b&e;b=a|b;#5c=b;d=#6ce;endThealwaysclauseaboveillustratestheothertypeofmethodofuse,i.e.itexecuteswheneveranyoftheentitiesinthelist(thebore)changes.Whenoneofthesechanges,aisimmediatelyassignedanewvalue,andduetotheblockingassignment,bisassignedanewvalueafterward(takingintoaccountthenewvalueofa).Afteradelayof5timeunits,cisassignedthevalueofbandthevalueofceistuckedawayinaninvisiblestore.Thenafter6moretimeunits,disassignedthevaluethatwastuckedaway.Signalsthataredrivenfromwithinaprocess(aninitialoralwaysblock)mustbeoftypereg.Signalsthataredrivenfromoutsideaprocessmustbeoftypewire.Thekeywordregdoesnotnecessarilyimplyahardwareregister.