Introduction to WAT Test SystemOutlineWhy WAT?Hardware SystemSoftware SystemTest Pattern and MeasurementWAT Testing FlowWAT Acceptance CriteriaWhat is WAT ?Wafer Acceptance TestWhat kind of work?An electrical test system, non-productivity activityWAT is an electrical test system for process goodness monitor.( Device characteristics, resistor, capacitor, interconnection, continuity, spacing, insulation, leakage)WAT is the primary quality element for a foundry FAB ( the quality assurance for wafer output) WAT characteristics: DC force and measurement, Automation, high throughput, precision, samplingWhy WATMonitor Process Window.Check Design Rule.Control the Process Parameters(SPC).Debug the Process Error.Reliability Characterization.Device Modeling for Circuit Design.Develop next Generation.WAT Testing SystemHardware System- Auto Test System- Manual SystemAutomatic Testing system for productionAutomatic TesterS630 (Keithley)4072A (Agilent)Automatic ProberP8-XL (TEL)UF200 (TSK)Server (workstation)SUNHPProber CardKeithleyAgilentAuto Probing SystemProberServerTesterTester HeadAuto Tester FunctionForce voltage, current.Measure voltage, current.Capacitance measure.Control prober movingA switch matrix to provide more than 48 pin output.Agilent Tester 4072AWorkstation34584284Power Supply81110Cooling FanSystem CabinetTestheadDiag BoardCPUInputSelector8 AUXPorts8 SMUGNDUPulse Switch6 HF PortMatrixOptical InterfaceKeithley Tester S630CabinetTest HeadTest Head of 4072A48 Pin48 inputExtended PathAUX PortHF PortPulseSwitch PortTest Head of S630PowerEMOTest Head of S630Test Head of S630Pre-AmplifyKeithley SMUSource Measurement Unit . Source High . Sense High Pin . Source/Sense LowGuardAuto Prober FunctionWafer load, unload & transfer to chuck.Prober Card Wafer pre-alignment, precise alignment.Test Line locate.Chuck up(probed)Chuck down(un-probed) TEL Prober P8-XLTEL Prober P12-XLTSK prober UF300Agilent 4072 + TEL P8-XLTester Head4072AControllerScreenWaferLoaderTouchPannelAuto WaferChangerAgilent 4072 + TSK UF300Keithley S630 + TEL P8-XLProber & Prober CardProber Card of Agilent4073ABird CageStructureDirect Dockingstructure Direct Docking+Fully GuardedFully Guarded+ +New MaterialNew Material4062UX4071/72AProber Card of AgilentProber Card of KeithleyFor Coax Epoxy and Ceramic Blade:Device soldered to underside of top board of probe cardServerTESTER 1Test HeadProberWaferProbe cardChuckController1WAT serverController 2Controller 3CIMWAT NetworkingWAT Operating FlowMain programPIL filePut Cassette on P8Use controller toAccess Main programWAT serverKey in product dataWAT serverInitialization (controller, tester, prober co-work)Controller: store raw dataProber: Move(test block, line)Tester: Force and measureTest Finish load data to serverServer upload data to intranetEDA database, WAT reportManual Testing System for engineeringIV Meter4200 (Keithley)4156 (Agilent)CV Meter4284 (Agilent)590 (Keithley)Switch MatrixE5250 (Agilent)790 (Keithley)Manual ProberS1170 (Sigatone)R4800 (Cascade)Manual Probing SystemIV MeterManualProberDark BoxManual Probing SystemManualProberCV MeterAgilent 4284Agilent Manual Test System IV Tester4156CCV Meter4284SwitchE5250Cofe BreakSoftware System- Auto Test System- Manual SystemSoftware of Auto TersterKeithley Keithley Test EnvironmentAgilent Semiconductor Process Evaluation Core SoftwareSPECS WorkCIMOperator ModeEngineering ModeRemote ExecutionAlgorithm LibraryRun Time AnalysisDatabaseSPECS FrameworkTest PlanNavigatorWaferSpecificationDieSpecificationProbeSpecificationTestSpecificationPIL FilePIL (Product Information List)One file to uni-control the product information which will be used in test.Such as:Step SizeModule Position5 Sites LocationTest ProgramLimit FileLimit FileWatch SystemTo watch if the raw data is out of Limit File.To watch if the raw data is out of the Warning Rule or Holding Rule.Send E-mail automatically to inform customer pay attention to this issue lot WAT TestingSite & Test LineTest line ATest line BTest line DTest lineCTest line ETest line FTest PatternTest key:Usually inside chip, for design rule check, yield monitor and process qualification and development.Can check subground rule.H27H271291018Test PatternTest line:Usually on scribe line. These pattern will be destroyed after die saw.For production monitorTL0018AUTL0018AU.12322WAT Parameter PreviewProcess Part:Spacing (Bridge,short)Continuity (Open)IsolationSheet RsContact RcKelvin Structure for ResistanceIntegrity (Inter layer dielectric)Extension rule checkCD measurementJunction leakageDevice Part:Gm (Vth,Current Gain)Idsat (Asym)IoffSwingGamma factorBKVIsubLeff,Rext,WeffField Device testCapacitanceReportDaily, weekly, monthlyCustomer, Eng-1 lot ownerIT Data ServerYMSWAT Testing FlowWAT Acceptance CriteriaWAT Sampling WAT test every wafer.WAT test 5 sites per wafer.WAT test each critical item in each testing site.A Critical Item mean one test parameter refers to customer product specification. WAT Fail DefinationItem FailIf there is a test parameter out of product specification, then this item fail.Site FailIf there is one or more items failure of one site, then this site fail.Wafer FailIf there are three or more sites failure of one Wafer, then this wafer fail.WAT Acceptance RuleWAT will not accept three or more Site Fail wafer.WAT will accept two or less Site Fail wafer.WAT fail wafer disposition will follow WAT Abnormal Disposition ProcedureWAT accepted wafer will transport to the next step. WAT Failure AnalysisWAT Re-TESTManual MeasurementSearched on the PromisTrack-in, track-out timing check.(Issue stage)Hold reason check.Process flow check.Equipment alarm check and Sorting.In-line check.(View Chartand so on)STR lotSEM and TEM checkWAT Parameters ReviewSpeaker: Alan Huang2024/9/25TopicWhy WAT?WAT Parameter Review.1)Process test Methodology.2)Device test Methodology.3)Process Factor Influence on WAT Para.Device CategorizationActive Device MOSFET(N/P),Field Transistor,BJT,DiodePassive Device Resistor,CapacitorsDesign rules Isolation,lines(Spacing,Continuity) contact,extensionResistorDiffusion regions N+,N-,P+,N-Well,P-Well,Deep-NWThin films P1,P2,M1,M2,M3Contact: C3 to N+/P+,Via C3 to P1,P2Process Part:(1) Spacing (Bridge,short)Define：验证在Process中，同层/同层之间的隔绝能力!Measurement method：Force 1uA电流到导线上，假若线路中有short，则测量出的电压值就偏低(50的结构中, Force I=0.01uA and Voltage lim=10V!(Req=L/W) Pad1Pad2Pad3Pad41um15um70um2um(W)70um1000LProcess Part:(7) Integrity(Gate-Oxide-Integrity)Define:验证Gate oxide 的Quality 好坏之一项参数当Gate oxide uniformity不均,或Interface间有defects时,会形成一漏电流路径失去Oxide Isolation的能力！Measurement method:一般测量法不外乎Force V/I and measure I/V1. Force V and measure I: Sweep Volt on Poly gate,and Vb=ground then measure Ig(aboutpA),If Ig increase to 1uA,this Sweep Volt is BKV(normal large 7 V)2. Force I and measure V: Force 1uA on Poly gate then measure VoltagePS:测量方式取决于Pattern design (common pad issue)WELLPoly GateProcess Part:(8) Extension rule checkDefine：以sense漏电流的方式，测量Contact overlay 的Design rule check!PS：(1) 一般来说，layout 的结构会采用十字架的形式，最大的好处是在把shot issues 的问题抓出! (2) miss-align 与contact number无关！M2ViaM1M1 ext to via用Poly4垫Process Part: (9) CD measurementDefine: 籍由测量两条同长度，不同宽度的电阻，换算出其宽度CD大小！PS: 当W=W1时 可测量得电阻R1 W=W2时 可测量得电阻R2 R1=Rs*L/(W1-W)R2=Rs*L/(W2- W)R1/R2=(W2- W) /(W1-W) 则W(CD loss),Rs皆可求得！ (P1 CD 大小影响到Channel length的长短,需特别注意）Process Part:(10) Junction leakageDefine：一般来说leakage指的是反向偏压时的漏电流测量，通常有以下三种分类： 1.Contact leak 2.Dielectric leak (usually for DRAM)3.Junction leak (bulk or peri)PS: I-bulk(meas)=A-bulk*J-area(current/um2)+L-peri*J-peri(current/um) I-finger(meas)=A-fing*J-area(current/um2)+L-peri(current/um) (J-area,J-peri 可求）PW拉出NAA有打Blanket N+impN-impC3M1Device Part:1)Gm (Vth,Current Gain)Define:Gm=(Id/ Vg)a)Linear:Id=1/2(CoxW/L)(2(Vgs-Vt)Vds-Vds2)Gm= CoxW/L b)Saturation:Id=1/2(CoxW/L)(Vgs-Vt)2Gm= CoxW/L(Vgs-Vt)c)Pinch-Off:Vds=Vgs-VtGm= Cox(W/L)Vds= Cox(W/L)PS:If value abnormal,It may have Gox, Leff or implant issues.Vth Measure method:Step1:Vds=0.1 Vs=Vb=0 and swoop VgStep2:Plot Ids Vgs and Gm Vgs curvesStep3:find Gm(max),plot slop of this point on Ids VgsFrom Linear function set Id=0then Vth=Vgs-V03VgIdDevice Part:2)Idsat (Asym)Define: Idsat=Ids at Vgs=Vds=VccIds Measure method:Step1:Vs=Vb=0,Vd=Vcc and Sweep VgStep2:Plot Ids VgsStep3:Find Ids at Vg=Vd=VccIds Asymmetry check:Step1:Following the Ids measurement.Step2:Change Drain and Source Pin-assign,then measure Ids.Step3:Asym=ABS(Ids-Ids)/IdsPS:If Ids Asymmetry Avnormal, It may have the Isub,(or Poly gate non-overlap issues)or LDD N-Rs, or Contact Rc some things trouble!ASMU2VgGDSSubVsubSMU3IdVdSMU1Device Part:3)IoffDefine: Ids=Ioff at Vgs=Vs=Vb=0,Vds=VccIoff Measure method (Direct meas.):Step1:Vs=Vb=0,Vd=Vcc and Sweep VgStep2:Plot Ids VgsStop3:Find Ids at Vg=0Ps: 测量机台的灵敏度，须注意与曲线的相 关联性！Ioff Measure method (外插法外插法):Step1:Follow the Ioff Direct meas.methodStep2:Plot Max slop of this curve on log(Ids) VgsStep3:Find the Ids at Vg=0 intercept.logIdVgVd=VcclogIdVgVd=VccDevice Part:4)Swing (Subthreshold Slop,St)Define:Swing=(log(Ids)/ Vgs)-1=2(kt/q)(1+Cd/Cox)*当Vg逐渐增加,channel accumulationdeplationweak inversionstrong inversion,Swing既是测量weak inversion时Id与Vg的变化程度!(exponential)DIBl effect measurement:Step1:Vs=Vb=,Vd= and Sweep VgStep2:Plot log(Ids) VgsStep3:Plot Max slop of this curve on log(Ids) VgsStep4:Repeat (a) but Vd=VccStep5:Repeat (b),PS:如果发生punch-through (Subsurface-DIBL),High drain St will larger than Low drain. (Swing越大 ,Leakage越大 )01VDS=5VVDS=0.1VVGIDDevice Part:5)Gamma factorDefine:=(2qNa1/2/Cox=Vt/(2f+Vbs1)1/2 -(2f+Vbs2) 1/2) Vt=Vf+2f+(2qNb(2f+Vsb)1/2/Cox*Gamma factor是在计算Substrate与Source间非等电位时，对Vt变化的影响.(Vt值需依Vbs的大小改变来计算)Measurement method:Step1:Fixed Vd=VStep2:Measure Vt under various Substate bias.Step3:Plot Vt versus(2f+Vbs)1/2 curveStep4:slope of the curve is taken to be Gammar factor.PS:Vt adjusment, Deep implant, well implant, well implant都会影响此一参数，通常Vt浓度越高，值越大!同理，不同的device在相同的Back-bias测量下，Vt差值，亦代表着值的影响VDVGN2N1Device Part:6)BKVDefine:Drain voltage which produces 1uA Drain Current.Breakdown Voltage是用来 test MOS的耐压程度。(1) 在Long channel的Device，看的是S/D to well 间junction的崩溃电压(2) 在Short channel的status，看到的BKV，有可 能是来自drain to source因punch-through造成 的低电压现象!PS:可籍由Id流到Is or Ib来判断BKV由何种造成！Measurement method:Step1:Vs=Vg=Vb=VStep2:set up Drain current limited at 1uA.Step3:Plot Ids VdsStep4:Sweep Vd and find the Voltage at Id =1uAN+N+VSVGVDVBDevice Part:7)IsubDefine:Isub (Measure MOS hot carrier effect.)Isub=f( Vds,Vgs)(1)Vds 对Isub impact:Pinch off point VDsat=Vgs VtIf Vds,VD-Vdsat then Emax,Isub(2)Vgs对Isub impact:一开始Vgs,Id then Isub,但当过pinch off point时 Vgs ,VD-Vdsat,then Emax IsubMeasurement method:Step1:Vs=Vb=0V,and Vd=VccStep2:Sweep Vg (Vgmin1/2Vd)Step3:Plot Isub VgsStep4:Isub=IsubmaxPS:If Isub abnormal, it may cause from hot carrier, Poly gate non-overlap,Contact over etchingand so on.AVgGDSSubIsubSMU3IdVdSMU2SMU1AVsubMeasurement Circuit0Method, CharacteristicsIsubVgPeak PointVg limit=VdDevice Part:8)Leff,Weff and RextDefine: Leff=Lmask-2L,Rext=Rm- Rchannel,Weff=Wmask-2 W公式推导：公式推导：IDS=(Weff/Leff)*Cox*n*(Vgs-Vt-0.5VDS )VDSRch=VDS/IDS=Leff/(Weff*Cox*n*(Vgs-Vt-0.5VDS)Rm=Vf/Im=Rext+Rch=Rext+A(Lmask-2L)A=1/(Weff *Cox*n*(Vgs-Vt-0.5VDS)Measurement method:Step1:Fixed VDS=0.1V,Vb=Vs=0VStep2:变化Vgs-Vt=2,3VStep3:Plot Rm LmaskStep4:选相同的Channel Width不同的length的device测量不同的 Vgs-Vt Bias 下的IDS,计算Rm=VDS/IDSStep5:计算两直线交点 X轴截距=2 L (2W 算法同） Y轴截距=Rext 01432567Rext=1650100150200VDS=0.1VVgS=0VGS=6VVGS=8VVGS=10VVGS=12VVGS=14VDevice Part:9)Field Device testDefine:测量Active region与field oxide 所 形成的寄生元件之Isolation能力测 试！考虑不同的 layout结构，有以下两种测量法：Measurement method:(1)Field Oxide上有导电材料覆盖： 此结构如同一AMOS元件，MOS Vt的大小，即反映出Field Isolation能力的好坏！ PS: 测量方法同Vth测量法！(2) Field oxide 上无导电材料覆盖： 此结构考虑Acitve range 间implant浓度的Isolation能力，一般是测量Constant current(1uA)下的耐压度 PolyAAFOXDevice Part:10)Capacitance (thickness meas)Define:电容的结构常见的有一般介质电 容与MOS电容两大类，差别在参 考极板的组成成分！Measurement method: (HP4284)(1) For 一般介质电容： Force Voltage的极性与电容大小无关！(2) for MOS电容： Gox电容的测量方面，要避免空乏层 电容的形成，才能算出Thickness Poly on PW:加负压于Poly gate 上,PW 接地！ Poly on NW:加正压于Poly gate 上,NW 接地！Process Factor influence on WAT ParaThreshold Voltage (Vt=VFB+/-(2F+QBO/COX)QBO=(2qNB(2F+VSB)1/2(1) NB(Well and Sub Con.),QBO,Vt(2) Gate Oxide (a)Thickness:tox,COX,Vt (b)Quality:Qfc,Vt(VFB= ms-Qfc/COX)(3) Vt adjust (Vt imp,deep-imp.)(4) Poly1 CD(Leff),QBO,Vt(for short channel)(5) S/D implant,Vt(For short channel)Process Factor influence on WAT ParaGain factor:=COX(W/L)1)Mobility ,Id a)GOX/Si interface quality,mobility,current Gain b)Cannel implant Dose,mobility,current Gain2)P1 CD,L,current Gain3)GOX thickness,COX,current GainGAMMA FACTOR NB ,COX(GOX thickness较厚), =（2qNB)1/2/COX =Vt/(2f+Vbs1)1/2-(2f+Vbs2)1/2)Process Factor influence on WAT ParaSaturation Current:Id=1/2(COXW/L)(Vgs-Vt)21)Vt implant,Isat2) GOX thickness,COX,Isat 3) Effective channel length Leff, Isat a)Poly1 CD (define Leff),Isat b)S/D implant c)Thermal Budget, Isat(Lateral Diffusion)4) Weff, Isat a)Nitride CD,Weff, Isat b)Birds beak encorach , IsatProcess Error Debugging1)WAT Re-TEST and Bench Meas2)Searched on the Promisa)Track-in, track-out timing check.(Issue stage)b)Hold reason check.c)Process flow check.d)Equipment alarm check and Sorting.e)In-line check.(View Chartand so on)f)STR lot3)SEM and TEM check